| Message ID | 20230919-optimize_checksum-v7-2-06c7d0ddd5d6@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: Add fine-tuned checksum functions | expand |
On Tue, Sep 19, 2023 at 11:44:31AM -0700, Charlie Jenkins wrote: > Provide checksum algorithms that have been designed to leverage riscv > instructions such as rotate. In 64-bit, can take advantage of the larger > register to avoid some overflow checking. > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Same here, Acked-by: Conor Dooley <conor.dooley@microchip.com> I think there are some "issues" attributed to this patch by the automation - but they spurious. This diff here could not cause a drivers/block/drbd/drbd_bitmap.c:1271: warning: Function parameter or member 'peer_device' not described in 'drbd_bm_write_copy_pages' after all. Cheers, Conor. > --- > arch/riscv/include/asm/checksum.h | 79 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 79 insertions(+) > > diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/checksum.h > new file mode 100644 > index 000000000000..dc0dd89f2a13 > --- /dev/null > +++ b/arch/riscv/include/asm/checksum.h > @@ -0,0 +1,79 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * IP checksum routines > + * > + * Copyright (C) 2023 Rivos Inc. > + */ > +#ifndef __ASM_RISCV_CHECKSUM_H > +#define __ASM_RISCV_CHECKSUM_H > + > +#include <linux/in6.h> > +#include <linux/uaccess.h> > + > +#define ip_fast_csum ip_fast_csum > + > +#include <asm-generic/checksum.h> > + > +/* > + * Quickly compute an IP checksum with the assumption that IPv4 headers will > + * always be in multiples of 32-bits, and have an ihl of at least 5. > + * @ihl is the number of 32 bit segments and must be greater than or equal to 5. > + * @iph is assumed to be word aligned. > + */ > +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) > +{ > + unsigned long csum = 0; > + int pos = 0; > + > + do { > + csum += ((const unsigned int *)iph)[pos]; > + if (IS_ENABLED(CONFIG_32BIT)) > + csum += csum < ((const unsigned int *)iph)[pos]; > + } while (++pos < ihl); > + > + /* > + * ZBB only saves three instructions on 32-bit and five on 64-bit so not > + * worth checking if supported without Alternatives. > + */ > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > + unsigned long fold_temp; > + > + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, > + RISCV_ISA_EXT_ZBB, 1) > + : > + : > + : > + : no_zbb); > + > + if (IS_ENABLED(CONFIG_32BIT)) { > + asm(".option push \n\ > + .option arch,+zbb \n\ > + not %[fold_temp], %[csum] \n\ > + rori %[csum], %[csum], 16 \n\ > + sub %[csum], %[fold_temp], %[csum] \n\ > + .option pop" > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > + } else { > + asm(".option push \n\ > + .option arch,+zbb \n\ > + rori %[fold_temp], %[csum], 32 \n\ > + add %[csum], %[fold_temp], %[csum] \n\ > + srli %[csum], %[csum], 32 \n\ > + not %[fold_temp], %[csum] \n\ > + roriw %[csum], %[csum], 16 \n\ > + subw %[csum], %[fold_temp], %[csum] \n\ > + .option pop" > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > + } > + return csum >> 16; > + } > +no_zbb: > +#ifndef CONFIG_32BIT > + csum += (csum >> 32) | (csum << 32); > + csum >>= 32; > +#endif > + return csum_fold((__force __wsum)csum); > +} > + > +#endif // __ASM_RISCV_CHECKSUM_H > > -- > 2.42.0 >
Hi Charlie, > -----Original Message----- > From: linux-riscv <linux-riscv-bounces@lists.infradead.org> On Behalf Of > Charlie Jenkins > Sent: Wednesday, September 20, 2023 2:45 AM > To: Charlie Jenkins <charlie@rivosinc.com>; Palmer Dabbelt > <palmer@dabbelt.com>; Conor Dooley <conor@kernel.org>; Samuel Holland > <samuel.holland@sifive.com>; David Laight <David.Laight@aculab.com>; > linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; linux- > arch@vger.kernel.org > Cc: Paul Walmsley <paul.walmsley@sifive.com>; Albert Ou > <aou@eecs.berkeley.edu>; Arnd Bergmann <arnd@arndb.de> > Subject: [PATCH v7 2/4] riscv: Checksum header > > Provide checksum algorithms that have been designed to leverage riscv > instructions such as rotate. In 64-bit, can take advantage of the larger > register to avoid some overflow checking. > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> > --- > arch/riscv/include/asm/checksum.h | 79 > +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 79 insertions(+) > > diff --git a/arch/riscv/include/asm/checksum.h > b/arch/riscv/include/asm/checksum.h > new file mode 100644 > index 000000000000..dc0dd89f2a13 > --- /dev/null > +++ b/arch/riscv/include/asm/checksum.h > @@ -0,0 +1,79 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * IP checksum routines > + * > + * Copyright (C) 2023 Rivos Inc. > + */ > +#ifndef __ASM_RISCV_CHECKSUM_H > +#define __ASM_RISCV_CHECKSUM_H > + > +#include <linux/in6.h> > +#include <linux/uaccess.h> > + > +#define ip_fast_csum ip_fast_csum > + > +#include <asm-generic/checksum.h> > + > +/* > + * Quickly compute an IP checksum with the assumption that IPv4 headers > will > + * always be in multiples of 32-bits, and have an ihl of at least 5. > + * @ihl is the number of 32 bit segments and must be greater than or equal > to 5. > + * @iph is assumed to be word aligned. Not sure if the assumption is always true. It looks the implementation in "lib/checksum.c" doesn't take this assumption. The ip header can comes after a 14-Byte ether header, which may start from a word-aligned or DMA friendly address. > + */ > +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) > +{ > + unsigned long csum = 0; > + int pos = 0; > + > + do { > + csum += ((const unsigned int *)iph)[pos]; > + if (IS_ENABLED(CONFIG_32BIT)) > + csum += csum < ((const unsigned int *)iph)[pos]; > + } while (++pos < ihl); > + > + /* > + * ZBB only saves three instructions on 32-bit and five on 64-bit so not > + * worth checking if supported without Alternatives. > + */ > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > + unsigned long fold_temp; > + > + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, > + RISCV_ISA_EXT_ZBB, 1) > + : > + : > + : > + : no_zbb); > + > + if (IS_ENABLED(CONFIG_32BIT)) { > + asm(".option push \n\ > + .option arch,+zbb \n\ > + not %[fold_temp], %[csum] > \n\ > + rori %[csum], %[csum], 16 \n\ > + sub %[csum], %[fold_temp], %[csum] > \n\ > + .option pop" > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > + } else { > + asm(".option push \n\ > + .option arch,+zbb \n\ > + rori %[fold_temp], %[csum], 32 \n\ > + add %[csum], %[fold_temp], %[csum] > \n\ > + srli %[csum], %[csum], 32 \n\ > + not %[fold_temp], %[csum] > \n\ > + roriw %[csum], %[csum], 16 \n\ > + subw %[csum], %[fold_temp], %[csum] > \n\ > + .option pop" > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > + } > + return csum >> 16; > + } > +no_zbb: > +#ifndef CONFIG_32BIT > + csum += (csum >> 32) | (csum << 32); Just like patch 3/4 does, we can call ror64(csum, 32). BRs, Xiao > + csum >>= 32; > +#endif > + return csum_fold((__force __wsum)csum); > +} > + > +#endif // __ASM_RISCV_CHECKSUM_H > > -- > 2.42.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, Oct 25, 2023 at 06:50:05AM +0000, Wang, Xiao W wrote: > Hi Charlie, > > > -----Original Message----- > > From: linux-riscv <linux-riscv-bounces@lists.infradead.org> On Behalf Of > > Charlie Jenkins > > Sent: Wednesday, September 20, 2023 2:45 AM > > To: Charlie Jenkins <charlie@rivosinc.com>; Palmer Dabbelt > > <palmer@dabbelt.com>; Conor Dooley <conor@kernel.org>; Samuel Holland > > <samuel.holland@sifive.com>; David Laight <David.Laight@aculab.com>; > > linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; linux- > > arch@vger.kernel.org > > Cc: Paul Walmsley <paul.walmsley@sifive.com>; Albert Ou > > <aou@eecs.berkeley.edu>; Arnd Bergmann <arnd@arndb.de> > > Subject: [PATCH v7 2/4] riscv: Checksum header > > > > Provide checksum algorithms that have been designed to leverage riscv > > instructions such as rotate. In 64-bit, can take advantage of the larger > > register to avoid some overflow checking. > > > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> > > --- > > arch/riscv/include/asm/checksum.h | 79 > > +++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 79 insertions(+) > > > > diff --git a/arch/riscv/include/asm/checksum.h > > b/arch/riscv/include/asm/checksum.h > > new file mode 100644 > > index 000000000000..dc0dd89f2a13 > > --- /dev/null > > +++ b/arch/riscv/include/asm/checksum.h > > @@ -0,0 +1,79 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * IP checksum routines > > + * > > + * Copyright (C) 2023 Rivos Inc. > > + */ > > +#ifndef __ASM_RISCV_CHECKSUM_H > > +#define __ASM_RISCV_CHECKSUM_H > > + > > +#include <linux/in6.h> > > +#include <linux/uaccess.h> > > + > > +#define ip_fast_csum ip_fast_csum > > + > > +#include <asm-generic/checksum.h> > > + > > +/* > > + * Quickly compute an IP checksum with the assumption that IPv4 headers > > will > > + * always be in multiples of 32-bits, and have an ihl of at least 5. > > + * @ihl is the number of 32 bit segments and must be greater than or equal > > to 5. > > + * @iph is assumed to be word aligned. > > Not sure if the assumption is always true. It looks the implementation in "lib/checksum.c" doesn't take this assumption. > The ip header can comes after a 14-Byte ether header, which may start from a word-aligned or DMA friendly address. While lib/checksum.c does not make this assumption, other architectures (x86, ARM, powerpc, mips, arc) do make this assumption. Architectures seem to only align the header on a word boundary in do_csum. I worry that the benefit of aligning iph in this "fast" csum function would disproportionately impact hardware that has fast misaligned accesses. - Charlie > > > + */ > > +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) > > +{ > > + unsigned long csum = 0; > > + int pos = 0; > > + > > + do { > > + csum += ((const unsigned int *)iph)[pos]; > > + if (IS_ENABLED(CONFIG_32BIT)) > > + csum += csum < ((const unsigned int *)iph)[pos]; > > + } while (++pos < ihl); > > + > > + /* > > + * ZBB only saves three instructions on 32-bit and five on 64-bit so not > > + * worth checking if supported without Alternatives. > > + */ > > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && > > + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { > > + unsigned long fold_temp; > > + > > + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, > > + RISCV_ISA_EXT_ZBB, 1) > > + : > > + : > > + : > > + : no_zbb); > > + > > + if (IS_ENABLED(CONFIG_32BIT)) { > > + asm(".option push \n\ > > + .option arch,+zbb \n\ > > + not %[fold_temp], %[csum] > > \n\ > > + rori %[csum], %[csum], 16 \n\ > > + sub %[csum], %[fold_temp], %[csum] > > \n\ > > + .option pop" > > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > > + } else { > > + asm(".option push \n\ > > + .option arch,+zbb \n\ > > + rori %[fold_temp], %[csum], 32 \n\ > > + add %[csum], %[fold_temp], %[csum] > > \n\ > > + srli %[csum], %[csum], 32 \n\ > > + not %[fold_temp], %[csum] > > \n\ > > + roriw %[csum], %[csum], 16 \n\ > > + subw %[csum], %[fold_temp], %[csum] > > \n\ > > + .option pop" > > + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); > > + } > > + return csum >> 16; > > + } > > +no_zbb: > > +#ifndef CONFIG_32BIT > > + csum += (csum >> 32) | (csum << 32); > > Just like patch 3/4 does, we can call ror64(csum, 32). > > BRs, > Xiao > > > + csum >>= 32; > > +#endif > > + return csum_fold((__force __wsum)csum); > > +} > > + > > +#endif // __ASM_RISCV_CHECKSUM_H > > > > -- > > 2.42.0 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, Oct 25, 2023, at 22:37, Charlie Jenkins wrote: > On Wed, Oct 25, 2023 at 06:50:05AM +0000, Wang, Xiao W wrote: >> > + >> > +/* >> > + * Quickly compute an IP checksum with the assumption that IPv4 headers >> > will >> > + * always be in multiples of 32-bits, and have an ihl of at least 5. >> > + * @ihl is the number of 32 bit segments and must be greater than or equal >> > to 5. >> > + * @iph is assumed to be word aligned. >> >> Not sure if the assumption is always true. It looks the implementation in "lib/checksum.c" doesn't take this assumption. >> The ip header can comes after a 14-Byte ether header, which may start from a word-aligned or DMA friendly address. > > While lib/checksum.c does not make this assumption, other architectures > (x86, ARM, powerpc, mips, arc) do make this assumption. Architectures > seem to only align the header on a word boundary in do_csum. I worry > that the benefit of aligning iph in this "fast" csum function would > disproportionately impact hardware that has fast misaligned accesses. Most architectures set NET_IP_ALIGN to '2', which is intended to have the IP header at a 32-bit aligned address, though some other targets don't bother: arch/arm64/include/asm/processor.h:#define NET_IP_ALIGN 0 arch/powerpc/include/asm/processor.h:#define NET_IP_ALIGN 0 arch/x86/include/asm/processor.h:#define NET_IP_ALIGN 0 include/linux/skbuff.h:#define NET_IP_ALIGN 2 I think it's considered a driver bug if an SKB ends up with a misaligned IP header, but it's also something that some of the more obscure drivers get wrong. Arnd
On Wed, Oct 25, 2023 at 10:52:22PM +0200, Arnd Bergmann wrote: > On Wed, Oct 25, 2023, at 22:37, Charlie Jenkins wrote: > > On Wed, Oct 25, 2023 at 06:50:05AM +0000, Wang, Xiao W wrote: > > >> > + > >> > +/* > >> > + * Quickly compute an IP checksum with the assumption that IPv4 headers > >> > will > >> > + * always be in multiples of 32-bits, and have an ihl of at least 5. > >> > + * @ihl is the number of 32 bit segments and must be greater than or equal > >> > to 5. > >> > + * @iph is assumed to be word aligned. > >> > >> Not sure if the assumption is always true. It looks the implementation in "lib/checksum.c" doesn't take this assumption. > >> The ip header can comes after a 14-Byte ether header, which may start from a word-aligned or DMA friendly address. > > > > While lib/checksum.c does not make this assumption, other architectures > > (x86, ARM, powerpc, mips, arc) do make this assumption. Architectures > > seem to only align the header on a word boundary in do_csum. I worry > > that the benefit of aligning iph in this "fast" csum function would > > disproportionately impact hardware that has fast misaligned accesses. > > Most architectures set NET_IP_ALIGN to '2', which is intended > to have the IP header at a 32-bit aligned address, though > some other targets don't bother: > > arch/arm64/include/asm/processor.h:#define NET_IP_ALIGN 0 > arch/powerpc/include/asm/processor.h:#define NET_IP_ALIGN 0 > arch/x86/include/asm/processor.h:#define NET_IP_ALIGN 0 > include/linux/skbuff.h:#define NET_IP_ALIGN 2 > > I think it's considered a driver bug if an SKB ends up > with a misaligned IP header, but it's also something that > some of the more obscure drivers get wrong. > > Arnd Thank you for pointing that out, I had not realized that macro existed. Since riscv keeps NET_IP_ALIGN at 0 it should be expected that ip_fast_csum is only called with 32-bit aligned addresses. I will update the comment and refer to that macro. riscv supports misaligned accesses but there are no guarantees of speed. - Charlie
On Wed, Oct 25, 2023, at 23:11, Charlie Jenkins wrote: > > Thank you for pointing that out, I had not realized that macro existed. > Since riscv keeps NET_IP_ALIGN at 0 it should be expected that > ip_fast_csum is only called with 32-bit aligned addresses. I will update > the comment and refer to that macro. riscv supports misaligned accesses > but there are no guarantees of speed. Just to clarify for your comment: riscv gets the default value of '2', which is the one that makes the header aligned. Arnd
On Wed, Oct 25, 2023 at 11:18:40PM +0200, Arnd Bergmann wrote: > On Wed, Oct 25, 2023, at 23:11, Charlie Jenkins wrote: > > > > Thank you for pointing that out, I had not realized that macro existed. > > Since riscv keeps NET_IP_ALIGN at 0 it should be expected that > > ip_fast_csum is only called with 32-bit aligned addresses. I will update > > the comment and refer to that macro. riscv supports misaligned accesses > > but there are no guarantees of speed. > > Just to clarify for your comment: riscv gets the default value of '2', > which is the one that makes the header aligned. > > Arnd Oops, typo. I meant to write 2. - Charlie
diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/checksum.h new file mode 100644 index 000000000000..dc0dd89f2a13 --- /dev/null +++ b/arch/riscv/include/asm/checksum.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * IP checksum routines + * + * Copyright (C) 2023 Rivos Inc. + */ +#ifndef __ASM_RISCV_CHECKSUM_H +#define __ASM_RISCV_CHECKSUM_H + +#include <linux/in6.h> +#include <linux/uaccess.h> + +#define ip_fast_csum ip_fast_csum + +#include <asm-generic/checksum.h> + +/* + * Quickly compute an IP checksum with the assumption that IPv4 headers will + * always be in multiples of 32-bits, and have an ihl of at least 5. + * @ihl is the number of 32 bit segments and must be greater than or equal to 5. + * @iph is assumed to be word aligned. + */ +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) +{ + unsigned long csum = 0; + int pos = 0; + + do { + csum += ((const unsigned int *)iph)[pos]; + if (IS_ENABLED(CONFIG_32BIT)) + csum += csum < ((const unsigned int *)iph)[pos]; + } while (++pos < ihl); + + /* + * ZBB only saves three instructions on 32-bit and five on 64-bit so not + * worth checking if supported without Alternatives. + */ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { + unsigned long fold_temp; + + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, + RISCV_ISA_EXT_ZBB, 1) + : + : + : + : no_zbb); + + if (IS_ENABLED(CONFIG_32BIT)) { + asm(".option push \n\ + .option arch,+zbb \n\ + not %[fold_temp], %[csum] \n\ + rori %[csum], %[csum], 16 \n\ + sub %[csum], %[fold_temp], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); + } else { + asm(".option push \n\ + .option arch,+zbb \n\ + rori %[fold_temp], %[csum], 32 \n\ + add %[csum], %[fold_temp], %[csum] \n\ + srli %[csum], %[csum], 32 \n\ + not %[fold_temp], %[csum] \n\ + roriw %[csum], %[csum], 16 \n\ + subw %[csum], %[fold_temp], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp)); + } + return csum >> 16; + } +no_zbb: +#ifndef CONFIG_32BIT + csum += (csum >> 32) | (csum << 32); + csum >>= 32; +#endif + return csum_fold((__force __wsum)csum); +} + +#endif // __ASM_RISCV_CHECKSUM_H
Provide checksum algorithms that have been designed to leverage riscv instructions such as rotate. In 64-bit, can take advantage of the larger register to avoid some overflow checking. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- arch/riscv/include/asm/checksum.h | 79 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+)