diff mbox series

[v3,1/2] RISC-V: Provide pgtable_l5_enabled on rv32

Message ID 20230925152409.29057-2-palmer@rivosinc.com (mailing list archive)
State Accepted
Commit 67ec9dfb762a7ba708053e87aa81e745c3a54507
Headers show
Series riscv: correct pt_level name via pgtable_l5/4_enabled | expand

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conchuod/fixes_present success Fixes tag present in non-next series
conchuod/maintainers_pattern success MAINTAINERS pattern errors before the patch: 5 and now 5
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conchuod/kdoc success Errors and warnings before: 0 this patch: 0
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conchuod/build_rv64_gcc_allmodconfig success Errors and warnings before: 1386 this patch: 1386
conchuod/build_rv32_defconfig success Build OK
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conchuod/patch-1-test-13 success .github/scripts/patches/verify_signedoff.sh
conchuod/patch-1-test-1 success .github/scripts/patches/build_rv32_defconfig.sh
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conchuod/patch-1-test-4 success .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
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conchuod/patch-1-test-9 success .github/scripts/patches/kdoc.sh
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Commit Message

Palmer Dabbelt Sept. 25, 2023, 3:22 p.m. UTC
A few of the other page table level helpers are defined on rv32, but not
pgtable_l5_enabled.  This adds the definition as a constant and converts
pgtable_l4_enabled to a constant as well.

Link: https://lore.kernel.org/r/20230830044129.11481-2-palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
 arch/riscv/include/asm/pgtable-32.h | 3 +++
 arch/riscv/include/asm/pgtable.h    | 1 -
 arch/riscv/mm/init.c                | 2 ++
 3 files changed, 5 insertions(+), 1 deletion(-)

Comments

Alexandre Ghiti Sept. 28, 2023, 8:13 a.m. UTC | #1
Hi Palmer,

On 25/09/2023 17:22, Palmer Dabbelt wrote:
> A few of the other page table level helpers are defined on rv32, but not
> pgtable_l5_enabled.  This adds the definition as a constant and converts
> pgtable_l4_enabled to a constant as well.
>
> Link: https://lore.kernel.org/r/20230830044129.11481-2-palmer@rivosinc.com
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
>   arch/riscv/include/asm/pgtable-32.h | 3 +++
>   arch/riscv/include/asm/pgtable.h    | 1 -
>   arch/riscv/mm/init.c                | 2 ++
>   3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
> index 59ba1fbaf784..00f3369570a8 100644
> --- a/arch/riscv/include/asm/pgtable-32.h
> +++ b/arch/riscv/include/asm/pgtable-32.h
> @@ -33,4 +33,7 @@
>   					  _PAGE_WRITE | _PAGE_EXEC |	\
>   					  _PAGE_USER | _PAGE_GLOBAL))
>   
> +static const __maybe_unused int pgtable_l4_enabled;
> +static const __maybe_unused int pgtable_l5_enabled;


pgtable_l4_enabled and pgtable_l5_enabled are boolean, not int.


> +
>   #endif /* _ASM_RISCV_PGTABLE_32_H */
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index b2ba3f79cfe9..e05e5c8f6526 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -914,7 +914,6 @@ extern uintptr_t _dtb_early_pa;
>   #define dtb_early_pa	_dtb_early_pa
>   #endif /* CONFIG_XIP_KERNEL */
>   extern u64 satp_mode;
> -extern bool pgtable_l4_enabled;


Isn't it easier to add pgtable_l5_enabled here ^


>   
>   void paging_init(void);
>   void misc_mem_init(void);
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index 0798bd861dcb..eed1758720c9 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -49,10 +49,12 @@ u64 satp_mode __ro_after_init = SATP_MODE_32;
>   #endif
>   EXPORT_SYMBOL(satp_mode);
>   
> +#ifdef CONFIG_64BIT
>   bool pgtable_l4_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL);
>   bool pgtable_l5_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL);
>   EXPORT_SYMBOL(pgtable_l4_enabled);
>   EXPORT_SYMBOL(pgtable_l5_enabled);
> +#endif
>   


And remove the #ifdef?


>   phys_addr_t phys_ram_base __ro_after_init;
>   EXPORT_SYMBOL(phys_ram_base);
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index 59ba1fbaf784..00f3369570a8 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -33,4 +33,7 @@ 
 					  _PAGE_WRITE | _PAGE_EXEC |	\
 					  _PAGE_USER | _PAGE_GLOBAL))
 
+static const __maybe_unused int pgtable_l4_enabled;
+static const __maybe_unused int pgtable_l5_enabled;
+
 #endif /* _ASM_RISCV_PGTABLE_32_H */
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index b2ba3f79cfe9..e05e5c8f6526 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -914,7 +914,6 @@  extern uintptr_t _dtb_early_pa;
 #define dtb_early_pa	_dtb_early_pa
 #endif /* CONFIG_XIP_KERNEL */
 extern u64 satp_mode;
-extern bool pgtable_l4_enabled;
 
 void paging_init(void);
 void misc_mem_init(void);
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 0798bd861dcb..eed1758720c9 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -49,10 +49,12 @@  u64 satp_mode __ro_after_init = SATP_MODE_32;
 #endif
 EXPORT_SYMBOL(satp_mode);
 
+#ifdef CONFIG_64BIT
 bool pgtable_l4_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL);
 bool pgtable_l5_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL);
 EXPORT_SYMBOL(pgtable_l4_enabled);
 EXPORT_SYMBOL(pgtable_l5_enabled);
+#endif
 
 phys_addr_t phys_ram_base __ro_after_init;
 EXPORT_SYMBOL(phys_ram_base);