diff mbox series

[v1,13/13] dt-bindings: riscv: add Zvfh[min] ISA extension description

Message ID 20231011111438.909552-14-cleger@rivosinc.com (mailing list archive)
State Superseded
Headers show
Series riscv: report more ISA extensions through hwprobe | expand

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail merge-conflict
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-13-test-1 success .github/scripts/patches/build_rv32_defconfig.sh
conchuod/patch-13-test-2 success .github/scripts/patches/build_rv64_clang_allmodconfig.sh
conchuod/patch-13-test-3 success .github/scripts/patches/build_rv64_gcc_allmodconfig.sh
conchuod/patch-13-test-4 success .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-13-test-5 success .github/scripts/patches/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-13-test-6 success .github/scripts/patches/checkpatch.sh
conchuod/patch-13-test-7 success .github/scripts/patches/dtb_warn_rv64.sh
conchuod/patch-13-test-8 success .github/scripts/patches/header_inline.sh
conchuod/patch-13-test-9 success .github/scripts/patches/kdoc.sh
conchuod/patch-13-test-10 success .github/scripts/patches/module_param.sh
conchuod/patch-13-test-11 success .github/scripts/patches/verify_fixes.sh
conchuod/patch-13-test-12 success .github/scripts/patches/verify_signedoff.sh

Commit Message

Clément Léger Oct. 11, 2023, 11:14 a.m. UTC
Add description for Zvfh[min] ISA extension[1] which can now be
reported through hwprobe for userspace usage.

[1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 .../devicetree/bindings/riscv/extensions.yaml        | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Conor Dooley Oct. 12, 2023, 1:51 p.m. UTC | #1
On Wed, Oct 11, 2023 at 01:14:38PM +0200, Clément Léger wrote:
> Add description for Zvfh[min] ISA extension[1] which can now be
> reported through hwprobe for userspace usage.
> 
> [1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view

And once more, the same.
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> 
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> ---
>  .../devicetree/bindings/riscv/extensions.yaml        | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 70c2b0351357..ae7db420ab92 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -277,6 +277,18 @@ properties:
>              instructions, as ratified in commit 56ed795 ("Update
>              riscv-crypto-spec-vector.adoc") of riscv-crypto.
>  
> +        - const: zvfh
> +          description:
> +            The standard Zvfh extension for vectored half-precision
> +            floating-point instructions, as ratified in commit e2ccd05
> +            ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
> +
> +        - const: zvfhmin
> +          description:
> +            The standard Zvfhmin extension for vectored minimal half-precision
> +            floating-point instructions, as ratified in commit e2ccd05
> +            ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
> +
>          - const: zvkb
>            description:
>              The standard Zvkb extension for vector cryptography bit-manipulation
> -- 
> 2.42.0
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 70c2b0351357..ae7db420ab92 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -277,6 +277,18 @@  properties:
             instructions, as ratified in commit 56ed795 ("Update
             riscv-crypto-spec-vector.adoc") of riscv-crypto.
 
+        - const: zvfh
+          description:
+            The standard Zvfh extension for vectored half-precision
+            floating-point instructions, as ratified in commit e2ccd05
+            ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
+
+        - const: zvfhmin
+          description:
+            The standard Zvfhmin extension for vectored minimal half-precision
+            floating-point instructions, as ratified in commit e2ccd05
+            ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
+
         - const: zvkb
           description:
             The standard Zvkb extension for vector cryptography bit-manipulation