[GIT,PULL] RISC-V Devicetrees for v6.6-final

Message ID	20231015-outmatch-tragedy-228f91d396b5@spud (mailing list archive)
State	Handled Elsewhere
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> Date: Sun, 15 Oct 2023 13:26:47 +0100 From: Conor Dooley <conor@kernel.org> To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V Devicetrees for v6.6-final Message-ID: <20231015-outmatch-tragedy-228f91d396b5@spud> MIME-Version: 1.0 Precedence: list Content-Type: multipart/mixed; boundary="===============1442334446967725168==" Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	[GIT,PULL] RISC-V Devicetrees for v6.6-final \| expand [GIT,PULL] RISC-V Devicetrees for v6.6-final

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20231015-outmatch-tragedy-228f91d396b5@spud (mailing list archive)

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Date: Sun, 15 Oct 2023 13:26:47 +0100
From: Conor Dooley <conor@kernel.org>
To: soc@kernel.org
Cc: conor@kernel.org, linux-riscv@lists.infradead.org
Subject: [GIT PULL] RISC-V Devicetrees for v6.6-final
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[GIT,PULL] RISC-V Devicetrees for v6.6-final | expand

Context	Check	Description
conchuod/vmtest-fixes-PR	fail	merge-conflict

Context

Check

Description

conchuod/vmtest-fixes-PR

fail

merge-conflict

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Conor Dooley Oct. 15, 2023, 12:26 p.m. UTC

Hey Arnd,

Just a single patch for you here, been quiet on the fixes front :)

Thanks,
Conor.

The following changes since commit 1558209533f140624a00408bdab796ab3f309450:

  riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order (2023-09-13 14:24:56 +0100)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-dt-for-v6.6-final

for you to fetch changes up to cf98fe6b579e55aa71b6197e34c112b51f0c2a66:

  riscv: dts: starfive: visionfive 2: correct spi's ss pin (2023-10-12 10:23:23 +0100)

----------------------------------------------------------------
RISC-V Devicetrees for v6.6-final

A single fix for the Starfive VisionFive 2 platform so that chip select
for SPI matches the vendor documentation.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

----------------------------------------------------------------
Nam Cao (1):
      riscv: dts: starfive: visionfive 2: correct spi's ss pin

 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

[GIT,PULL] RISC-V Devicetrees for v6.6-final

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