diff mbox series

[v2,03/10] irqchip/riscv-intc: Introduce Andes IRQ chip

Message ID 20231019135723.3657156-1-peterlin@andestech.com (mailing list archive)
State Superseded
Headers show
Series Support Andes PMU extension | expand

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail merge-conflict

Commit Message

Yu Chien Peter Lin Oct. 19, 2023, 1:57 p.m. UTC 
This commit adds support for the Andes IRQ chip, which provides
IRQ mask/unmask functions to access the custom CSR (SLIE)
where the non-standard S-mode local interrupt enable bits are
located.

The Andes INTC requires the "andestech,cpu-intc" compatible string
to be present in interrupt-controller of each cpu node. e.g.,

  cpu0: cpu@0 {
      compatible = "andestech,ax45mp", "riscv";
      ...
      cpu0-intc: interrupt-controller {
          #interrupt-cells = <0x01>;
          compatible = "andestech,cpu-intc";
          interrupt-controller;
      };
  };

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
  - New patch
---
 drivers/irqchip/irq-riscv-intc.c       | 49 ++++++++++++++++++++++++--
 include/linux/irqchip/irq-riscv-intc.h | 12 +++++++
 2 files changed, 59 insertions(+), 2 deletions(-)
 create mode 100644 include/linux/irqchip/irq-riscv-intc.h

Comments

Thomas Gleixner Oct. 27, 2023, 7:08 a.m. UTC | #1 
On Thu, Oct 19 2023 at 21:57, Yu Chien Peter Lin wrote:
> This commit adds support for the Andes IRQ chip, which provides

"This commit" is not any different from "This patch" and equaly
pointless. See Documentation/process/submitting-patches.rst

Also please write out interrupt instead of IRQ. Changelogs are text and
not subject to twitter limitations.

> IRQ mask/unmask functions to access the custom CSR (SLIE)

What is a CSR? These acronyms are really annoying for people who are not
familiar with the chip specific details.

> +static void andes_intc_irq_mask(struct irq_data *d)
> +{
> +	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
> +
> +	if (d->hwirq < ANDES_SLI_CAUSE_BASE)

This lacks a comment which explains why these hardware interrupts are
special.

> +		csr_clear(CSR_IE, mask);
> +	else
> +		csr_clear(ANDES_CSR_SLIE, mask);
> +}
> +
> +static void andes_intc_irq_unmask(struct irq_data *d)
> +{
> +	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
> +
> +	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> +		csr_set(CSR_IE, mask);
> +	else
> +		csr_set(ANDES_CSR_SLIE, mask);
> +}
> +
>  static void riscv_intc_irq_eoi(struct irq_data *d)
>  {
>  	/*
> @@ -68,12 +89,35 @@ static struct irq_chip riscv_intc_chip = {
>  	.irq_eoi = riscv_intc_irq_eoi,
>  };
>  
> +static struct irq_chip andes_intc_chip = {
> +	.name = "RISC-V INTC",
> +	.irq_mask = andes_intc_irq_mask,
> +	.irq_unmask = andes_intc_irq_unmask,
> +	.irq_eoi = riscv_intc_irq_eoi,

https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers

> +};
> +
>  static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
>  				 irq_hw_number_t hwirq)
>  {
> +	struct fwnode_handle *fn = riscv_get_intc_hwnode();
> +	struct irq_chip *chip;
> +	const char *cp;
> +	int rc;
> +
>  	irq_set_percpu_devid(irq);

Why is this not moved after the failure condition too?

> -	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
> -			    handle_percpu_devid_irq, NULL, NULL);
> +
> +	rc = fwnode_property_read_string(fn, "compatible", &cp);
> +	if (rc)
> +		return rc;
> +
> +	if (strcmp(cp, "riscv,cpu-intc") == 0)
> +		chip = &riscv_intc_chip;
> +	else if (strcmp(cp, "andestech,cpu-intc") == 0)
> +		chip = &andes_intc_chip;

How is this supposed to work with ACPI?

The obvious solution for this is to have two different init functions

riscv_intc_init()
{
        riscv_intc_init_common(..., &risc_intc_chip);
}

riscv_andes_init()
{
        riscv_intc_init_common(..., &andes_intc_chip);
}

riscv_intc_init_common(...., *chip)
{
        // Set the interrupt chip pointer as domain host data
        irqdomain_create_linear(...., chip);
}

and then you can use that in the map function:

    chip = domain->host_data;

See?

> diff --git a/include/linux/irqchip/irq-riscv-intc.h b/include/linux/irqchip/irq-riscv-intc.h
> new file mode 100644
> index 000000000000..87c105b5b545
> --- /dev/null
> +++ b/include/linux/irqchip/irq-riscv-intc.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2023 Andes Technology Corporation
> + */
> +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H
> +#define __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H
> +
> +#define ANDES_SLI_CAUSE_BASE	256
> +#define ANDES_CSR_SLIE		0x9c4
> +#define ANDES_CSR_SLIP		0x9c5
> +
> +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H */

What's the purpose of this header file? The defines are only used in the
interrupt chip driver code, so they can just be in the C file. No?

Thanks,

        tglx
Yu Chien Peter Lin Oct. 30, 2023, 6:43 a.m. UTC | #2 
Hi Thomas,

On Fri, Oct 27, 2023 at 09:08:56AM +0200, Thomas Gleixner wrote:
> On Thu, Oct 19 2023 at 21:57, Yu Chien Peter Lin wrote:
> > This commit adds support for the Andes IRQ chip, which provides
> 
> "This commit" is not any different from "This patch" and equaly
> pointless. See Documentation/process/submitting-patches.rst

Sure, will rewrite the commit message.
Thanks for the pointer.

> Also please write out interrupt instead of IRQ. Changelogs are text and
> not subject to twitter limitations.

OK!

> > IRQ mask/unmask functions to access the custom CSR (SLIE)
> 
> What is a CSR? These acronyms are really annoying for people who are not
> familiar with the chip specific details.

OK!

> > +static void andes_intc_irq_mask(struct irq_data *d)
> > +{
> > +	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
> > +
> > +	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> 
> This lacks a comment which explains why these hardware interrupts are
> special.

Sure, will add a comment here.

> > +		csr_clear(CSR_IE, mask);
> > +	else
> > +		csr_clear(ANDES_CSR_SLIE, mask);
> > +}
> > +
> > +static void andes_intc_irq_unmask(struct irq_data *d)
> > +{
> > +	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
> > +
> > +	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
> > +		csr_set(CSR_IE, mask);
> > +	else
> > +		csr_set(ANDES_CSR_SLIE, mask);
> > +}
> > +
> >  static void riscv_intc_irq_eoi(struct irq_data *d)
> >  {
> >  	/*
> > @@ -68,12 +89,35 @@ static struct irq_chip riscv_intc_chip = {
> >  	.irq_eoi = riscv_intc_irq_eoi,
> >  };
> >  
> > +static struct irq_chip andes_intc_chip = {
> > +	.name = "RISC-V INTC",
> > +	.irq_mask = andes_intc_irq_mask,
> > +	.irq_unmask = andes_intc_irq_unmask,
> > +	.irq_eoi = riscv_intc_irq_eoi,
> 
> https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers

OK, will fix.

> > +};
> > +
> >  static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
> >  				 irq_hw_number_t hwirq)
> >  {
> > +	struct fwnode_handle *fn = riscv_get_intc_hwnode();
> > +	struct irq_chip *chip;
> > +	const char *cp;
> > +	int rc;
> > +
> >  	irq_set_percpu_devid(irq);
> 
> Why is this not moved after the failure condition too?
> 
> > -	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
> > -			    handle_percpu_devid_irq, NULL, NULL);
> > +
> > +	rc = fwnode_property_read_string(fn, "compatible", &cp);
> > +	if (rc)
> > +		return rc;
> > +
> > +	if (strcmp(cp, "riscv,cpu-intc") == 0)
> > +		chip = &riscv_intc_chip;
> > +	else if (strcmp(cp, "andestech,cpu-intc") == 0)
> > +		chip = &andes_intc_chip;
> 
> How is this supposed to work with ACPI?
> 
> The obvious solution for this is to have two different init functions
> 
> riscv_intc_init()
> {
>         riscv_intc_init_common(..., &risc_intc_chip);
> }
> 
> riscv_andes_init()
> {
>         riscv_intc_init_common(..., &andes_intc_chip);
> }
> 
> riscv_intc_init_common(...., *chip)
> {
>         // Set the interrupt chip pointer as domain host data
>         irqdomain_create_linear(...., chip);
> }
> 
> and then you can use that in the map function:
> 
>     chip = domain->host_data;
> 
> See?

Got it! Will reimplement according to this method.

> > diff --git a/include/linux/irqchip/irq-riscv-intc.h b/include/linux/irqchip/irq-riscv-intc.h
> > new file mode 100644
> > index 000000000000..87c105b5b545
> > --- /dev/null
> > +++ b/include/linux/irqchip/irq-riscv-intc.h
> > @@ -0,0 +1,12 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2023 Andes Technology Corporation
> > + */
> > +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H
> > +#define __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H
> > +
> > +#define ANDES_SLI_CAUSE_BASE	256
> > +#define ANDES_CSR_SLIE		0x9c4
> > +#define ANDES_CSR_SLIP		0x9c5
> > +
> > +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H */
> 
> What's the purpose of this header file? The defines are only used in the
> interrupt chip driver code, so they can just be in the C file. No?
> 
> Thanks,

These definitions are shared with drivers/perf/riscv_pmu_sbi.c,
however, I should not add vendor specific things here, they
will be move to include/linux/soc/andes/irq.h.

Thanks for the review!

Best regards,
Peter Lin

>         tglx
>
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 79d049105384..fcd06b58bdac 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -13,6 +13,7 @@ 
 #include <linux/irq.h>
 #include <linux/irqchip.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/irq-riscv-intc.h>
 #include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/of.h>
@@ -45,6 +46,26 @@  static void riscv_intc_irq_unmask(struct irq_data *d)
 	csr_set(CSR_IE, BIT(d->hwirq));
 }
 
+static void andes_intc_irq_mask(struct irq_data *d)
+{
+	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+		csr_clear(CSR_IE, mask);
+	else
+		csr_clear(ANDES_CSR_SLIE, mask);
+}
+
+static void andes_intc_irq_unmask(struct irq_data *d)
+{
+	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+	if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+		csr_set(CSR_IE, mask);
+	else
+		csr_set(ANDES_CSR_SLIE, mask);
+}
+
 static void riscv_intc_irq_eoi(struct irq_data *d)
 {
 	/*
@@ -68,12 +89,35 @@  static struct irq_chip riscv_intc_chip = {
 	.irq_eoi = riscv_intc_irq_eoi,
 };
 
+static struct irq_chip andes_intc_chip = {
+	.name = "RISC-V INTC",
+	.irq_mask = andes_intc_irq_mask,
+	.irq_unmask = andes_intc_irq_unmask,
+	.irq_eoi = riscv_intc_irq_eoi,
+};
+
 static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
 				 irq_hw_number_t hwirq)
 {
+	struct fwnode_handle *fn = riscv_get_intc_hwnode();
+	struct irq_chip *chip;
+	const char *cp;
+	int rc;
+
 	irq_set_percpu_devid(irq);
-	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
-			    handle_percpu_devid_irq, NULL, NULL);
+
+	rc = fwnode_property_read_string(fn, "compatible", &cp);
+	if (rc)
+		return rc;
+
+	if (strcmp(cp, "riscv,cpu-intc") == 0)
+		chip = &riscv_intc_chip;
+	else if (strcmp(cp, "andestech,cpu-intc") == 0)
+		chip = &andes_intc_chip;
+
+	irq_domain_set_info(d, irq, hwirq, chip,
+			    d->host_data, handle_percpu_devid_irq, NULL,
+			    NULL);
 
 	return 0;
 }
@@ -166,6 +210,7 @@  static int __init riscv_intc_init(struct device_node *node,
 }
 
 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
+IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
 
 #ifdef CONFIG_ACPI
 
diff --git a/include/linux/irqchip/irq-riscv-intc.h b/include/linux/irqchip/irq-riscv-intc.h
new file mode 100644
index 000000000000..87c105b5b545
--- /dev/null
+++ b/include/linux/irqchip/irq-riscv-intc.h
@@ -0,0 +1,12 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H
+#define __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H
+
+#define ANDES_SLI_CAUSE_BASE	256
+#define ANDES_CSR_SLIE		0x9c4
+#define ANDES_CSR_SLIP		0x9c5
+
+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_RISCV_INTC_H */