| Message ID | 20231020-unrated-uproar-c911c6185ae9@spud (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | PolarFire SoC Auto Update Support | expand |
On Fri, Oct 20, 2023 at 02:18:44PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > The system controller's flash can be accessed via an MSS-exposed QSPI > controller sitting, which sits between the mailbox's control & data > registers. On Icicle, it has an MT25QL01GBBB8ESF connected to it. > > The system controller and MSS both have separate QSPI controllers, both > of which can access the flash, although the system controller takes > priority. > Unfortunately, on engineering sample silicon, such as that on Icicle > kits, the MSS' QSPI controller cannot write to the flash due to a bug. > As a workaround, a QSPI controller can be implemented in the FPGA > fabric and the IO routing modified to connect it to the flash in place > of the "hard" controller in the MSS. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../boot/dts/microchip/mpfs-icicle-kit.dts | 21 +++++++++++++++++++ > arch/riscv/boot/dts/microchip/mpfs.dtsi | 17 +++++++++++++++ > 2 files changed, 38 insertions(+) > > diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts > index 90b261114763..2dae3f8f33f6 100644 > --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts > +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts > @@ -199,6 +199,27 @@ &syscontroller { > status = "okay"; > }; > > +&syscontroller_qspi { > + /* > + * The flash *is* there, but Icicle kits that have engineering sample > + * silicon (write?) access to this flash to non-functional. The system > + * controller itself can actually access it, but the MSS cannot write > + * an image there. Instantiating a coreQSPI in the fabric & connecting > + * it to the flash instead should work though. Pre-production or later > + * silicon does not have this issue. > + */ > + status = "disabled"; > + > + sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT > + compatible = "jedec,spi-nor"; > + #address-cells = <1>; > + #size-cells = <1>; > + spi-max-frequency = <20000000>; > + spi-rx-bus-width = <1>; > + reg = <0>; > + }; > +}; Hmm, I think I will drop this part of the patch, and instead add the flash for the sev-kit (which does work correctly) to avoid any confusion as to why this is not supported on the current icicle kit boards. Cheers, Conor.
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index 90b261114763..2dae3f8f33f6 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -199,6 +199,27 @@ &syscontroller { status = "okay"; }; +&syscontroller_qspi { + /* + * The flash *is* there, but Icicle kits that have engineering sample + * silicon (write?) access to this flash to non-functional. The system + * controller itself can actually access it, but the MSS cannot write + * an image there. Instantiating a coreQSPI in the fabric & connecting + * it to the flash instead should work though. Pre-production or later + * silicon does not have this issue. + */ + status = "disabled"; + + sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <1>; + reg = <0>; + }; +}; + &usb { status = "okay"; dr_mode = "host"; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 104504352e99..8f66e2c839ef 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -178,6 +178,12 @@ syscontroller: syscontroller { mboxes = <&mbox 0>; }; + scbclk: mssclkclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -508,5 +514,16 @@ mbox: mailbox@37020000 { #mbox-cells = <1>; status = "disabled"; }; + + syscontroller_qspi: spi@37020100 { + compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x37020100 0x0 0x100>; + interrupt-parent = <&plic>; + interrupts = <110>; + clocks = <&scbclk>; + status = "disabled"; + }; }; };