diff mbox series

[v1] riscv: dts: microchip: move timebase-frequency to mpfs.dtsi

Message ID 20231126-unlighted-favorably-4627f2361a59@spud (mailing list archive)
State Accepted
Delegated to: Conor Dooley
Headers show
Series [v1] riscv: dts: microchip: move timebase-frequency to mpfs.dtsi | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR success PR summary
conchuod/patch-1-test-1 success .github/scripts/patches/build_rv32_defconfig.sh
conchuod/patch-1-test-2 success .github/scripts/patches/build_rv64_clang_allmodconfig.sh
conchuod/patch-1-test-3 success .github/scripts/patches/build_rv64_gcc_allmodconfig.sh
conchuod/patch-1-test-4 success .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-1-test-5 success .github/scripts/patches/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-1-test-6 success .github/scripts/patches/checkpatch.sh
conchuod/patch-1-test-7 success .github/scripts/patches/dtb_warn_rv64.sh
conchuod/patch-1-test-8 success .github/scripts/patches/header_inline.sh
conchuod/patch-1-test-9 success .github/scripts/patches/kdoc.sh
conchuod/patch-1-test-10 success .github/scripts/patches/module_param.sh
conchuod/patch-1-test-11 success .github/scripts/patches/verify_fixes.sh
conchuod/patch-1-test-12 success .github/scripts/patches/verify_signedoff.sh

Commit Message

Conor Dooley Nov. 26, 2023, 11:45 a.m. UTC 
From: Conor Dooley <conor.dooley@microchip.com>

The timebase-frequency on PolarFire SoC is not set by an oscillator on
the board, but rather by an internal divider, so move the property to
mpfs.dtsi.

This looks to be copy-pasta from the SiFive Unleashed as the comments
in both places were almost identical. In the Unleashed's case this looks
to actually be valid, as the clock is provided by a crystal on the PCB.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
CC: Conor Dooley <conor.dooley@microchip.com>
CC: Daire McNamara <daire.mcnamara@microchip.com>
CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
---
 arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 7 -------
 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts | 7 -------
 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 7 -------
 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts    | 7 -------
 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts    | 7 -------
 arch/riscv/boot/dts/microchip/mpfs.dtsi           | 1 +
 6 files changed, 1 insertion(+), 35 deletions(-)

Comments

Emil Renner Berthing Nov. 26, 2023, 3:35 p.m. UTC | #1 
Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The timebase-frequency on PolarFire SoC is not set by an oscillator on
> the board, but rather by an internal divider, so move the property to
> mpfs.dtsi.
>
> This looks to be copy-pasta from the SiFive Unleashed as the comments
> in both places were almost identical. In the Unleashed's case this looks
> to actually be valid, as the clock is provided by a crystal on the PCB.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Makes sense to me.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>

> ---
> CC: Conor Dooley <conor.dooley@microchip.com>
> CC: Daire McNamara <daire.mcnamara@microchip.com>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> CC: Paul Walmsley <paul.walmsley@sifive.com>
> CC: Palmer Dabbelt <palmer@dabbelt.com>
> CC: linux-riscv@lists.infradead.org
> CC: devicetree@vger.kernel.org
> ---
>  arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 7 -------
>  arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts | 7 -------
>  arch/riscv/boot/dts/microchip/mpfs-polarberry.dts | 7 -------
>  arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts    | 7 -------
>  arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts    | 7 -------
>  arch/riscv/boot/dts/microchip/mpfs.dtsi           | 1 +
>  6 files changed, 1 insertion(+), 35 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> index 90b261114763..dce96f27cc89 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> @@ -8,9 +8,6 @@
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/leds/common.h>
>
> -/* Clock frequency (in Hz) of the rtcclk */
> -#define RTCCLK_FREQ		1000000
> -
>  / {
>  	model = "Microchip PolarFire-SoC Icicle Kit";
>  	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
> @@ -29,10 +26,6 @@ chosen {
>  		stdout-path = "serial1:115200n8";
>  	};
>
> -	cpus {
> -		timebase-frequency = <RTCCLK_FREQ>;
> -	};
> -
>  	leds {
>  		compatible = "gpio-leds";
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
> index 184cb36a175e..a8d623ee9fa4 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
> @@ -10,9 +10,6 @@
>  #include "mpfs.dtsi"
>  #include "mpfs-m100pfs-fabric.dtsi"
>
> -/* Clock frequency (in Hz) of the rtcclk */
> -#define MTIMER_FREQ	1000000
> -
>  / {
>  	model = "Aries Embedded M100PFEVPS";
>  	compatible = "aries,m100pfsevp", "microchip,mpfs";
> @@ -33,10 +30,6 @@ chosen {
>  		stdout-path = "serial1:115200n8";
>  	};
>
> -	cpus {
> -		timebase-frequency = <MTIMER_FREQ>;
> -	};
> -
>  	ddrc_cache_lo: memory@80000000 {
>  		device_type = "memory";
>  		reg = <0x0 0x80000000 0x0 0x40000000>;
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> index c87cc2d8fe29..ea0808ab1042 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> @@ -6,9 +6,6 @@
>  #include "mpfs.dtsi"
>  #include "mpfs-polarberry-fabric.dtsi"
>
> -/* Clock frequency (in Hz) of the rtcclk */
> -#define MTIMER_FREQ	1000000
> -
>  / {
>  	model = "Sundance PolarBerry";
>  	compatible = "sundance,polarberry", "microchip,mpfs";
> @@ -22,10 +19,6 @@ chosen {
>  		stdout-path = "serial0:115200n8";
>  	};
>
> -	cpus {
> -		timebase-frequency = <MTIMER_FREQ>;
> -	};
> -
>  	ddrc_cache_lo: memory@80000000 {
>  		device_type = "memory";
>  		reg = <0x0 0x80000000 0x0 0x2e000000>;
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
> index 013cb666c72d..f9a890579438 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
> @@ -6,9 +6,6 @@
>  #include "mpfs.dtsi"
>  #include "mpfs-sev-kit-fabric.dtsi"
>
> -/* Clock frequency (in Hz) of the rtcclk */
> -#define MTIMER_FREQ		1000000
> -
>  / {
>  	#address-cells = <2>;
>  	#size-cells = <2>;
> @@ -28,10 +25,6 @@ chosen {
>  		stdout-path = "serial1:115200n8";
>  	};
>
> -	cpus {
> -		timebase-frequency = <MTIMER_FREQ>;
> -	};
> -
>  	reserved-memory {
>  		#address-cells = <2>;
>  		#size-cells = <2>;
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> index e0797c7e1b35..d1120f5f2c01 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
> @@ -11,9 +11,6 @@
>  #include "mpfs.dtsi"
>  #include "mpfs-tysom-m-fabric.dtsi"
>
> -/* Clock frequency (in Hz) of the rtcclk */
> -#define MTIMER_FREQ		1000000
> -
>  / {
>  	model = "Aldec TySOM-M-MPFS250T-REV2";
>  	compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
> @@ -34,10 +31,6 @@ chosen {
>  		stdout-path = "serial1:115200n8";
>  	};
>
> -	cpus {
> -		timebase-frequency = <MTIMER_FREQ>;
> -	};
> -
>  	ddrc_cache_lo: memory@80000000 {
>  		device_type = "memory";
>  		reg = <0x0 0x80000000 0x0 0x30000000>;
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index a6faf24f1dba..266489d43912 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -13,6 +13,7 @@ / {
>  	cpus {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> +		timebase-frequency = <1000000>;
>
>  		cpu0: cpu@0 {
>  			compatible = "sifive,e51", "sifive,rocket0", "riscv";
> --
> 2.39.2
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 90b261114763..dce96f27cc89 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -8,9 +8,6 @@ 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
 
-/* Clock frequency (in Hz) of the rtcclk */
-#define RTCCLK_FREQ		1000000
-
 / {
 	model = "Microchip PolarFire-SoC Icicle Kit";
 	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
@@ -29,10 +26,6 @@  chosen {
 		stdout-path = "serial1:115200n8";
 	};
 
-	cpus {
-		timebase-frequency = <RTCCLK_FREQ>;
-	};
-
 	leds {
 		compatible = "gpio-leds";
 
diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
index 184cb36a175e..a8d623ee9fa4 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
@@ -10,9 +10,6 @@ 
 #include "mpfs.dtsi"
 #include "mpfs-m100pfs-fabric.dtsi"
 
-/* Clock frequency (in Hz) of the rtcclk */
-#define MTIMER_FREQ	1000000
-
 / {
 	model = "Aries Embedded M100PFEVPS";
 	compatible = "aries,m100pfsevp", "microchip,mpfs";
@@ -33,10 +30,6 @@  chosen {
 		stdout-path = "serial1:115200n8";
 	};
 
-	cpus {
-		timebase-frequency = <MTIMER_FREQ>;
-	};
-
 	ddrc_cache_lo: memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x40000000>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
index c87cc2d8fe29..ea0808ab1042 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
@@ -6,9 +6,6 @@ 
 #include "mpfs.dtsi"
 #include "mpfs-polarberry-fabric.dtsi"
 
-/* Clock frequency (in Hz) of the rtcclk */
-#define MTIMER_FREQ	1000000
-
 / {
 	model = "Sundance PolarBerry";
 	compatible = "sundance,polarberry", "microchip,mpfs";
@@ -22,10 +19,6 @@  chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	cpus {
-		timebase-frequency = <MTIMER_FREQ>;
-	};
-
 	ddrc_cache_lo: memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x2e000000>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
index 013cb666c72d..f9a890579438 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
@@ -6,9 +6,6 @@ 
 #include "mpfs.dtsi"
 #include "mpfs-sev-kit-fabric.dtsi"
 
-/* Clock frequency (in Hz) of the rtcclk */
-#define MTIMER_FREQ		1000000
-
 / {
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -28,10 +25,6 @@  chosen {
 		stdout-path = "serial1:115200n8";
 	};
 
-	cpus {
-		timebase-frequency = <MTIMER_FREQ>;
-	};
-
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
index e0797c7e1b35..d1120f5f2c01 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
@@ -11,9 +11,6 @@ 
 #include "mpfs.dtsi"
 #include "mpfs-tysom-m-fabric.dtsi"
 
-/* Clock frequency (in Hz) of the rtcclk */
-#define MTIMER_FREQ		1000000
-
 / {
 	model = "Aldec TySOM-M-MPFS250T-REV2";
 	compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
@@ -34,10 +31,6 @@  chosen {
 		stdout-path = "serial1:115200n8";
 	};
 
-	cpus {
-		timebase-frequency = <MTIMER_FREQ>;
-	};
-
 	ddrc_cache_lo: memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x0 0x30000000>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index a6faf24f1dba..266489d43912 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -13,6 +13,7 @@  / {
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		timebase-frequency = <1000000>;
 
 		cpu0: cpu@0 {
 			compatible = "sifive,e51", "sifive,rocket0", "riscv";