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[v5,2/2] riscv: dts: starfive: jh8100: Add watchdog node

Message ID 20231221084358.3458713-3-jisheng.teoh@starfivetech.com (mailing list archive)
State Deferred
Delegated to: Conor Dooley
Headers show
Series Add StarFive JH8100 watchdog | expand

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail merge-conflict

Commit Message

Ji Sheng Teoh Dec. 21, 2023, 8:43 a.m. UTC
StarFive's JH8100 watchdog is based on JH7110, with JH8100 watchdog only
requiring one reset signal.

Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh8100.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
index 9863c61324a0..657d8b79e708 100644
--- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
@@ -360,6 +360,15 @@  uart4: serial@121a0000  {
 			status = "disabled";
 		};
 
+		watchdog@12270000 {
+			compatible = "starfive,jh8100-wdt", "starfive,jh7110-wdt";
+			reg = <0x0 0x12270000 0x0 0x10000>;
+			clocks = <&syscrg_ne SYSCRG_NE_CLK_WDT_APB>,
+				 <&syscrg_ne SYSCRG_NE_CLK_WDT>;
+			clock-names = "apb", "core";
+			resets = <&syscrg_ne SYSCRG_NE_RSTN_WDT0>;
+		};
+
 		syscrg_ne: syscrg_ne@12320000 {
 			compatible = "starfive,jh8100-syscrg-ne";
 			reg = <0x0 0x12320000 0x0 0x10000>;