| Message ID | 20240125062739.1339782-9-debug@rivosinc.com (mailing list archive) |
|---|---|
| State | RFC |
| Headers | show |
| Series | riscv control-flow integrity for usermode | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On 25.01.24 07:21, debug@rivosinc.com wrote: > From: Deepak Gupta <debug@rivosinc.com> > > VM_SHADOW_STACK is defined by x86 as vm flag to mark a shadow stack vma. > > x86 uses VM_HIGH_ARCH_5 bit but that limits shadow stack vma to 64bit only. > arm64 follows same path > https://lore.kernel.org/lkml/20231009-arm64-gcs-v6-12-78e55deaa4dd@kernel.org/#r > > On RISC-V, write-only page table encodings are shadow stack pages. This patch > re-defines VM_WRITE only to be VM_SHADOW_STACK. > > Next set of patches will set guard rail that no other mm flow can set VM_WRITE > only in vma except when specifically creating shadow stack. > > Signed-off-by: Deepak Gupta <debug@rivosinc.com> > --- > include/linux/mm.h | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/include/linux/mm.h b/include/linux/mm.h > index 418d26608ece..dfe0e8118669 100644 > --- a/include/linux/mm.h > +++ b/include/linux/mm.h > @@ -352,7 +352,19 @@ extern unsigned int kobjsize(const void *objp); > * for more details on the guard size. > */ > # define VM_SHADOW_STACK VM_HIGH_ARCH_5 > -#else > +#endif > + > +#ifdef CONFIG_RISCV_USER_CFI > +/* > + * On RISC-V pte encodings for shadow stack is R=0, W=1, X=0 and thus RISCV > + * choosing to use similar mechanism on vm_flags where VM_WRITE only means > + * VM_SHADOW_STACK. RISCV as well doesn't support VM_SHADOW_STACK to be set > + * with VM_SHARED. > + */ > +#define VM_SHADOW_STACK VM_WRITE > +#endif > + > +#ifndef VM_SHADOW_STACK > # define VM_SHADOW_STACK VM_NONE > #endif > That just screams for trouble. Can we find a less hacky way, please? Maybe just start with 64bit support only and do it like the other archs. No need to be special. When wanting to support 32bit, we'll just finally clean up this high flag mess and allow for more vm flags on 32bit as well.
On Thu, Jan 25, 2024 at 09:17:01AM +0100, David Hildenbrand wrote: >On 25.01.24 07:21, debug@rivosinc.com wrote: >>From: Deepak Gupta <debug@rivosinc.com> >> >>VM_SHADOW_STACK is defined by x86 as vm flag to mark a shadow stack vma. >> >>x86 uses VM_HIGH_ARCH_5 bit but that limits shadow stack vma to 64bit only. >>arm64 follows same path >>https://lore.kernel.org/lkml/20231009-arm64-gcs-v6-12-78e55deaa4dd@kernel.org/#r >> >>On RISC-V, write-only page table encodings are shadow stack pages. This patch >>re-defines VM_WRITE only to be VM_SHADOW_STACK. >> >>Next set of patches will set guard rail that no other mm flow can set VM_WRITE >>only in vma except when specifically creating shadow stack. >> >>Signed-off-by: Deepak Gupta <debug@rivosinc.com> >>--- >> include/linux/mm.h | 14 +++++++++++++- >> 1 file changed, 13 insertions(+), 1 deletion(-) >> >>diff --git a/include/linux/mm.h b/include/linux/mm.h >>index 418d26608ece..dfe0e8118669 100644 >>--- a/include/linux/mm.h >>+++ b/include/linux/mm.h >>@@ -352,7 +352,19 @@ extern unsigned int kobjsize(const void *objp); >> * for more details on the guard size. >> */ >> # define VM_SHADOW_STACK VM_HIGH_ARCH_5 >>-#else >>+#endif >>+ >>+#ifdef CONFIG_RISCV_USER_CFI >>+/* >>+ * On RISC-V pte encodings for shadow stack is R=0, W=1, X=0 and thus RISCV >>+ * choosing to use similar mechanism on vm_flags where VM_WRITE only means >>+ * VM_SHADOW_STACK. RISCV as well doesn't support VM_SHADOW_STACK to be set >>+ * with VM_SHARED. >>+ */ >>+#define VM_SHADOW_STACK VM_WRITE >>+#endif >>+ >>+#ifndef VM_SHADOW_STACK >> # define VM_SHADOW_STACK VM_NONE >> #endif > >That just screams for trouble. Can we find a less hacky way, please? > >Maybe just start with 64bit support only and do it like the other >archs. No need to be special. > >When wanting to support 32bit, we'll just finally clean up this high >flag mess and allow for more vm flags on 32bit as well. Noted. I wanted to give a chance to anyone who cares about 32bit on riscv. Will fix it in next series. > >-- >Cheers, > >David / dhildenb >
diff --git a/include/linux/mm.h b/include/linux/mm.h index 418d26608ece..dfe0e8118669 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -352,7 +352,19 @@ extern unsigned int kobjsize(const void *objp); * for more details on the guard size. */ # define VM_SHADOW_STACK VM_HIGH_ARCH_5 -#else +#endif + +#ifdef CONFIG_RISCV_USER_CFI +/* + * On RISC-V pte encodings for shadow stack is R=0, W=1, X=0 and thus RISCV + * choosing to use similar mechanism on vm_flags where VM_WRITE only means + * VM_SHADOW_STACK. RISCV as well doesn't support VM_SHADOW_STACK to be set + * with VM_SHARED. + */ +#define VM_SHADOW_STACK VM_WRITE +#endif + +#ifndef VM_SHADOW_STACK # define VM_SHADOW_STACK VM_NONE #endif