| Message ID | 20240125165416.1987576-1-leyfoon.tan@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clocksource: timer-riscv: Clear timer interrupt on timer initialization | expand |
On Thu, Jan 25, 2024 at 10:25 PM Ley Foon Tan <leyfoon.tan@starfivetech.com> wrote: > > In the RISC-V specification, the stimecmp register doesn't have a default > value. To prevent the timer interrupt from being triggered during timer > initialization, clear the timer interrupt by writing stimecmp with a > maximum value. > > Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > --- > drivers/clocksource/timer-riscv.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > index e66dcbd66566..a75a74647344 100644 > --- a/drivers/clocksource/timer-riscv.c > +++ b/drivers/clocksource/timer-riscv.c > @@ -172,6 +172,9 @@ static int __init riscv_timer_init_common(void) > > sched_clock_register(riscv_sched_clock, 64, riscv_timebase); > > + /* Clear timer interrupt */ > + riscv_clock_event_stop(); > + The riscv_timer_init_common() is called only on boot HART. I suggest doing riscv_clock_event_stop() in riscv_timer_starting_cpu() just before enable_percpu_irq(). I also suggest adding an appropriate Fixes tag in the commit description. Regards, Anup > error = request_percpu_irq(riscv_clock_event_irq, > riscv_timer_interrupt, > "riscv-timer", &riscv_clock_event); > -- > 2.43.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
> -----Original Message----- > From: Anup Patel <apatel@ventanamicro.com> > Sent: Friday, January 26, 2024 1:00 AM > To: Leyfoon Tan <leyfoon.tan@starfivetech.com> > Cc: Daniel Lezcano <daniel.lezcano@linaro.org>; Thomas Gleixner > <tglx@linutronix.de>; Palmer Dabbelt <palmer@dabbelt.com>; Paul Walmsley > <paul.walmsley@sifive.com>; Albert Ou <aou@eecs.berkeley.edu>; > atishp@rivosinc.com; linux-riscv@lists.infradead.org; linux- > kernel@vger.kernel.org; Ley Foon Tan <lftan.linux@gmail.com> > Subject: Re: [PATCH] clocksource: timer-riscv: Clear timer interrupt on timer > initialization > > On Thu, Jan 25, 2024 at 10:25 PM Ley Foon Tan > <leyfoon.tan@starfivetech.com> wrote: > > > > In the RISC-V specification, the stimecmp register doesn't have a > > default value. To prevent the timer interrupt from being triggered > > during timer initialization, clear the timer interrupt by writing > > stimecmp with a maximum value. > > > > Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > --- > > drivers/clocksource/timer-riscv.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/clocksource/timer-riscv.c > > b/drivers/clocksource/timer-riscv.c > > index e66dcbd66566..a75a74647344 100644 > > --- a/drivers/clocksource/timer-riscv.c > > +++ b/drivers/clocksource/timer-riscv.c > > @@ -172,6 +172,9 @@ static int __init riscv_timer_init_common(void) > > > > sched_clock_register(riscv_sched_clock, 64, riscv_timebase); > > > > + /* Clear timer interrupt */ > > + riscv_clock_event_stop(); > > + > > The riscv_timer_init_common() is called only on boot HART. > > I suggest doing riscv_clock_event_stop() in riscv_timer_starting_cpu() just > before enable_percpu_irq(). > > I also suggest adding an appropriate Fixes tag in the commit description. > > Regards, > Anup > Okay, will change it. Thanks. Regards Ley Foon
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index e66dcbd66566..a75a74647344 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -172,6 +172,9 @@ static int __init riscv_timer_init_common(void) sched_clock_register(riscv_sched_clock, 64, riscv_timebase); + /* Clear timer interrupt */ + riscv_clock_event_stop(); + error = request_percpu_irq(riscv_clock_event_irq, riscv_timer_interrupt, "riscv-timer", &riscv_clock_event);
In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> --- drivers/clocksource/timer-riscv.c | 3 +++ 1 file changed, 3 insertions(+)