diff mbox series

[v8,02/10] irqchip/riscv-intc: Allow large non-standard interrupt number

Message ID 20240129092553.2058043-3-peterlin@andestech.com (mailing list archive)
State Superseded
Headers show
Series Support Andes PMU extension | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-2-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh
conchuod/patch-2-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh
conchuod/patch-2-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh
conchuod/patch-2-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-2-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-2-test-6 success .github/scripts/patches/tests/checkpatch.sh
conchuod/patch-2-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh
conchuod/patch-2-test-8 success .github/scripts/patches/tests/header_inline.sh
conchuod/patch-2-test-9 success .github/scripts/patches/tests/kdoc.sh
conchuod/patch-2-test-10 success .github/scripts/patches/tests/module_param.sh
conchuod/patch-2-test-11 success .github/scripts/patches/tests/verify_fixes.sh
conchuod/patch-2-test-12 success .github/scripts/patches/tests/verify_signedoff.sh

Commit Message

Yu-Chien Peter Lin Jan. 29, 2024, 9:25 a.m. UTC 
Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as the hardware interrupt number, with a maximum of
64 interrupts. However, the platform can expand the interrupt number
further for custom local interrupts.

To fully utilize the available local interrupt sources, switch
to using irq_domain_create_tree() that creates the radix tree
map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
and riscv_intc_custom_nr_irqs) to determine the valid range of local
interrupt number (hwirq).

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
Changes v1 -> v2:
  - Fixed irq mapping failure checking (suggested by Clément and Anup)
Changes v2 -> v3:
  - No change
Changes v3 -> v4: (Suggested by Thomas [1])
  - Use pr_warn_ratelimited instead
  - Fix coding style and commit message
Changes v4 -> v5: (Suggested by Thomas)
  - Fix commit message
Changes v5 -> v6: (Suggested by Anup [2])
  - Add riscv_intc_* global variables for checking the range of valid
    interrupt number in riscv_intc_domain_alloc()
  - Advertise the number of interrupts allowed
Changes v6 -> v7:
  - No functional change
Changes v7 -> v8:
  - Include Reviewed-by tags from Anup and Atish

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20231023004100.2663486-3-peterlin@andestech.com/#25573085                                                                                         ..
[2] https://patchwork.kernel.org/project/linux-riscv/patch/20231213070301.1684751-3-peterlin@andestech.com/#25636589
---
 drivers/irqchip/irq-riscv-intc.c | 30 +++++++++++++++++++++++-------
 1 file changed, 23 insertions(+), 7 deletions(-)

Comments

Thomas Gleixner Feb. 13, 2024, 10:04 a.m. UTC | #1 
On Mon, Jan 29 2024 at 17:25, Yu Chien Peter Lin wrote:
>  static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
>  {
>  	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
>  
> -	if (unlikely(cause >= BITS_PER_LONG))
> -		panic("unexpected interrupt cause");
> -
> -	generic_handle_domain_irq(intc_domain, cause);
> +	if (generic_handle_domain_irq(intc_domain, cause))
> +		pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n",
> +				    cause);

Either let the cause stick out or you need brackets. See:

  https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#bracket-rules

>  }
>  
>  /*
> @@ -93,6 +95,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
>  	if (ret)
>  		return ret;
>  
> +	/*
> +	 * Only allow hwirq for which we have corresponding standard or
> +	 * custom interrupt enable register.
> +	 */
> +	if ((riscv_intc_nr_irqs <= hwirq && hwirq < riscv_intc_custom_base) ||
> +	    (riscv_intc_custom_base + riscv_intc_custom_nr_irqs) <= hwirq)
> +		return -EINVAL;

Duh. This mix of ordering required to read this 3 times. What's wrong
with writing this consistently:

	if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
	    (hwirq >= iscv_intc_custom_base + riscv_intc_custom_nr_irqs)
		return -EINVAL;

Hmm?

> -	pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
> +	pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
> +	if (riscv_intc_custom_nr_irqs)
> +		pr_info("%d custom local interrupts mapped\n",
> +			riscv_intc_custom_nr_irqs);

See bracket rules.
  
>  	return 0;
>  }
> @@ -166,6 +178,10 @@ static int __init riscv_intc_init(struct device_node *node,
>  		return 0;
>  	}
>  
> +	riscv_intc_nr_irqs = BITS_PER_LONG;
> +	riscv_intc_custom_base = riscv_intc_nr_irqs;

Why don't you initialize the static variables with constants right away?

> +	riscv_intc_custom_nr_irqs = 0;

It's already 0, no?

>  	return riscv_intc_init_common(of_node_to_fwnode(node));
>  }

Thanks,

        tglx
Yu-Chien Peter Lin Feb. 22, 2024, 3:25 a.m. UTC | #2 
Hi Thomas,

On Tue, Feb 13, 2024 at 11:04:53AM +0100, Thomas Gleixner wrote:
> On Mon, Jan 29 2024 at 17:25, Yu Chien Peter Lin wrote:
> >  static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
> >  {
> >  	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
> >  
> > -	if (unlikely(cause >= BITS_PER_LONG))
> > -		panic("unexpected interrupt cause");
> > -
> > -	generic_handle_domain_irq(intc_domain, cause);
> > +	if (generic_handle_domain_irq(intc_domain, cause))
> > +		pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n",
> > +				    cause);
> 
> Either let the cause stick out or you need brackets. See:
> 
>   https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#bracket-rules
> 
> >  }
> >  
> >  /*
> > @@ -93,6 +95,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
> >  	if (ret)
> >  		return ret;
> >  
> > +	/*
> > +	 * Only allow hwirq for which we have corresponding standard or
> > +	 * custom interrupt enable register.
> > +	 */
> > +	if ((riscv_intc_nr_irqs <= hwirq && hwirq < riscv_intc_custom_base) ||
> > +	    (riscv_intc_custom_base + riscv_intc_custom_nr_irqs) <= hwirq)
> > +		return -EINVAL;
> 
> Duh. This mix of ordering required to read this 3 times. What's wrong
> with writing this consistently:
> 
> 	if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
> 	    (hwirq >= iscv_intc_custom_base + riscv_intc_custom_nr_irqs)
> 		return -EINVAL;
> 
> Hmm?
> 
> > -	pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
> > +	pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
> > +	if (riscv_intc_custom_nr_irqs)
> > +		pr_info("%d custom local interrupts mapped\n",
> > +			riscv_intc_custom_nr_irqs);
> 
> See bracket rules.
>   
> >  	return 0;
> >  }
> > @@ -166,6 +178,10 @@ static int __init riscv_intc_init(struct device_node *node,
> >  		return 0;
> >  	}
> >  
> > +	riscv_intc_nr_irqs = BITS_PER_LONG;
> > +	riscv_intc_custom_base = riscv_intc_nr_irqs;
> 
> Why don't you initialize the static variables with constants right away?
> 
> > +	riscv_intc_custom_nr_irqs = 0;
> 
> It's already 0, no?
> 
> >  	return riscv_intc_init_common(of_node_to_fwnode(node));
> >  }
> 
> Thanks,
> 
>         tglx

Thanks for pointing these out, I'll fix them in PATCH v9.

Regards,
Peter Lin
diff mbox series

Patch

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b14ccdd..b13a16b164c9 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -19,15 +19,17 @@ 
 #include <linux/smp.h>
 
 static struct irq_domain *intc_domain;
+static unsigned int riscv_intc_nr_irqs __ro_after_init;
+static unsigned int riscv_intc_custom_base __ro_after_init;
+static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
 
 static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
 {
 	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
 
-	if (unlikely(cause >= BITS_PER_LONG))
-		panic("unexpected interrupt cause");
-
-	generic_handle_domain_irq(intc_domain, cause);
+	if (generic_handle_domain_irq(intc_domain, cause))
+		pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n",
+				    cause);
 }
 
 /*
@@ -93,6 +95,14 @@  static int riscv_intc_domain_alloc(struct irq_domain *domain,
 	if (ret)
 		return ret;
 
+	/*
+	 * Only allow hwirq for which we have corresponding standard or
+	 * custom interrupt enable register.
+	 */
+	if ((riscv_intc_nr_irqs <= hwirq && hwirq < riscv_intc_custom_base) ||
+	    (riscv_intc_custom_base + riscv_intc_custom_nr_irqs) <= hwirq)
+		return -EINVAL;
+
 	for (i = 0; i < nr_irqs; i++) {
 		ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
 		if (ret)
@@ -117,8 +127,7 @@  static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 {
 	int rc;
 
-	intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
-					       &riscv_intc_domain_ops, NULL);
+	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
 	if (!intc_domain) {
 		pr_err("unable to add IRQ domain\n");
 		return -ENXIO;
@@ -132,7 +141,10 @@  static int __init riscv_intc_init_common(struct fwnode_handle *fn)
 
 	riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
 
-	pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
+	pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
+	if (riscv_intc_custom_nr_irqs)
+		pr_info("%d custom local interrupts mapped\n",
+			riscv_intc_custom_nr_irqs);
 
 	return 0;
 }
@@ -166,6 +178,10 @@  static int __init riscv_intc_init(struct device_node *node,
 		return 0;
 	}
 
+	riscv_intc_nr_irqs = BITS_PER_LONG;
+	riscv_intc_custom_base = riscv_intc_nr_irqs;
+	riscv_intc_custom_nr_irqs = 0;
+
 	return riscv_intc_init_common(of_node_to_fwnode(node));
 }