Message ID | 20240312-fencei-v13-1-4b6bdc2bbf32@rivosinc.com (mailing list archive) |
---|---|
State | Accepted |
Commit | bebc345413f5fb4c8fafb59ff0bd8509197627e6 |
Headers | show |
Series | riscv: Create and document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl | expand |
diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 08d4d6a5b7e9..6fd8cbfcfcc7 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -7,7 +7,6 @@ #ifndef _ASM_RISCV_IRQFLAGS_H #define _ASM_RISCV_IRQFLAGS_H -#include <asm/processor.h> #include <asm/csr.h> /* read interrupt enabled status */