| Message ID | 20240409-silencer-book-ce1320f06aab@spud (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 81889e8523e63395b388f285c77ff0c98ea04556 |
| Headers | show |
| Series | RISC-V: enable rust | expand |
On Tue, 9 Apr 2024 18:25:16 +0100 Conor Dooley <conor@kernel.org> wrote: > From: Miguel Ojeda <ojeda@kernel.org> > > The rust modules work on 64-bit RISC-V, with no twiddling required. > Select HAVE_RUST and provide the required flags to kbuild so that the > modules can be used. The Makefile and Kconfig changes are lifted from > work done by Miguel in the Rust-for-Linux tree, hence his authorship. > Following the rabbit hole, the Makefile changes originated in a script, > created based on config files originally added by Gary, hence his > co-authorship. Thanks for sending the patch! > 32-bit is broken in core rust code, so support is limited to 64-bit: > ld.lld: error: undefined symbol: __udivdi3 I wouldn't call the core rust code broken :) The missing symbol here should be easily stubbed by changing the redirect-intrinsics in rust/Makefile and adding a stub in compiler_builtins.rs. Although we probably instead of panicking, want to redirect the division to kernel division routine (IIRC the division is used for formatting integers, which is a legit use of division). > > As 64-bit RISC-V is now supported, add it to the arch support table. > > Co-developed-by: Gary Guo <gary@garyguo.net> > Signed-off-by: Gary Guo <gary@garyguo.net> > Signed-off-by: Miguel Ojeda <ojeda@kernel.org> > Co-developed-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > Documentation/rust/arch-support.rst | 1 + > arch/riscv/Kconfig | 1 + > arch/riscv/Makefile | 7 +++++++ > scripts/generate_rust_target.rs | 6 ++++++ > 4 files changed, 15 insertions(+)
diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-support.rst index 5c4fa9f5d1cd..4d1495ded2aa 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -17,6 +17,7 @@ Architecture Level of support Constraints ============= ================ ============================================== ``arm64`` Maintained Little Endian only. ``loongarch`` Maintained - +``riscv`` Maintained ``riscv64`` only. ``um`` Maintained ``x86_64`` only. ``x86`` Maintained ``x86_64`` only. ============= ================ ============================================== diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index be09c8836d56..cad31864fd0f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -155,6 +155,7 @@ config RISCV select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RETHOOK if !XIP_KERNEL select HAVE_RSEQ + select HAVE_RUST if 64BIT select HAVE_SAMPLE_FTRACE_DIRECT select HAVE_SAMPLE_FTRACE_DIRECT_MULTI select HAVE_STACKPROTECTOR diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 252d63942f34..adbc9023d7f0 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -34,6 +34,9 @@ ifeq ($(CONFIG_ARCH_RV64I),y) KBUILD_AFLAGS += -mabi=lp64 KBUILD_LDFLAGS += -melf64lriscv + + KBUILD_RUSTFLAGS += -Ctarget-cpu=generic-rv64 --target=riscv64imac-unknown-none-elf \ + -Cno-redzone else BITS := 32 UTS_MACHINE := riscv32 @@ -68,6 +71,10 @@ riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v +ifneq ($(CONFIG_RISCV_ISA_C),y) + KBUILD_RUSTFLAGS += -Ctarget-feature=-c +endif + ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC KBUILD_CFLAGS += -Wa,-misa-spec=2.2 KBUILD_AFLAGS += -Wa,-misa-spec=2.2 diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs index 54919cf48621..8f7846b9029a 100644 --- a/scripts/generate_rust_target.rs +++ b/scripts/generate_rust_target.rs @@ -150,6 +150,12 @@ fn main() { // `llvm-target`s are taken from `scripts/Makefile.clang`. if cfg.has("ARM64") { panic!("arm64 uses the builtin rustc aarch64-unknown-none target"); + } else if cfg.has("RISCV") { + if cfg.has("64BIT") { + panic!("64-bit RISC-V uses the builtin rustc riscv64-unknown-none-elf target"); + } else { + panic!("32-bit RISC-V is an unsupported architecture"); + } } else if cfg.has("X86_64") { ts.push("arch", "x86_64"); ts.push(