diff mbox series

[v2,09/17] riscv: uaccess: Add alternative for xtheadvector uaccess

Message ID 20240415-dev-charlie-support_thead_vector_6_9-v2-9-c7d68c603268@rivosinc.com (mailing list archive)
State Superseded
Headers show
Series riscv: Support vendor extensions and xtheadvector | expand

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail merge-conflict
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-9-test-1 fail .github/scripts/patches/tests/build_rv32_defconfig.sh
conchuod/patch-9-test-2 fail .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh
conchuod/patch-9-test-3 fail .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh
conchuod/patch-9-test-4 fail .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-9-test-5 fail .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-9-test-6 warning .github/scripts/patches/tests/checkpatch.sh
conchuod/patch-9-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh
conchuod/patch-9-test-8 success .github/scripts/patches/tests/header_inline.sh
conchuod/patch-9-test-9 success .github/scripts/patches/tests/kdoc.sh
conchuod/patch-9-test-10 success .github/scripts/patches/tests/module_param.sh
conchuod/patch-9-test-11 success .github/scripts/patches/tests/verify_fixes.sh
conchuod/patch-9-test-12 success .github/scripts/patches/tests/verify_signedoff.sh

Commit Message

Charlie Jenkins April 16, 2024, 4:12 a.m. UTC 
At this time, use the fallback uaccess routines rather than customizing
the vectorized uaccess routines to be compatible with xtheadvector.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
 arch/riscv/lib/uaccess.S | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
index bc22c078aba8..1fe798666aee 100644
--- a/arch/riscv/lib/uaccess.S
+++ b/arch/riscv/lib/uaccess.S
@@ -5,6 +5,7 @@ 
 #include <asm/csr.h>
 #include <asm/hwcap.h>
 #include <asm/alternative-macros.h>
+#include <asm/vendorid_list.h>
 
 	.macro fixup op reg addr lbl
 100:
@@ -15,6 +16,7 @@ 
 SYM_FUNC_START(__asm_copy_to_user)
 #ifdef CONFIG_RISCV_ISA_V
 	ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_v, CONFIG_RISCV_ISA_V)
+	ALTERNATIVE("nop", "j fallback_scalar_usercopy", THEAD_VENDOR_ID, RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, CONFIG_RISCV_ISA_XTHEADVECTOR)
 	REG_L	t0, riscv_v_usercopy_threshold
 	bltu	a2, t0, fallback_scalar_usercopy
 	tail enter_vector_usercopy