| Message ID | 20240514104508.938448-3-prajna.rajendrakumar@microchip.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | Add support for GPIO based CS | expand |
On Tue, May 14, 2024 at 11:45:07AM +0100, Prajna Rajendra Kumar wrote: > The SPI "hard" controller in PolarFire SoC has eight CS lines, but only > one CS line is wired. When the 'num-cs' property is not specified in > the device tree, the driver defaults to the MAX_CS value, which has > been fixed to 1 to match the hardware configuration; however, when the > 'num-cs' property is explicitly defined in the device tree, it > overrides the default value. > > Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers") > Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> I gave you a reviewed-by on v1, here it is again: Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor. > --- > drivers/spi/spi-microchip-core.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c > index 634364c7cfe6..c10de45aa472 100644 > --- a/drivers/spi/spi-microchip-core.c > +++ b/drivers/spi/spi-microchip-core.c > @@ -21,7 +21,7 @@ > #include <linux/spi/spi.h> > > #define MAX_LEN (0xffff) > -#define MAX_CS (8) > +#define MAX_CS (1) > #define DEFAULT_FRAMESIZE (8) > #define FIFO_DEPTH (32) > #define CLK_GEN_MODE1_MAX (255) > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c index 634364c7cfe6..c10de45aa472 100644 --- a/drivers/spi/spi-microchip-core.c +++ b/drivers/spi/spi-microchip-core.c @@ -21,7 +21,7 @@ #include <linux/spi/spi.h> #define MAX_LEN (0xffff) -#define MAX_CS (8) +#define MAX_CS (1) #define DEFAULT_FRAMESIZE (8) #define FIFO_DEPTH (32) #define CLK_GEN_MODE1_MAX (255)
The SPI "hard" controller in PolarFire SoC has eight CS lines, but only one CS line is wired. When the 'num-cs' property is not specified in the device tree, the driver defaults to the MAX_CS value, which has been fixed to 1 to match the hardware configuration; however, when the 'num-cs' property is explicitly defined in the device tree, it overrides the default value. Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers") Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> --- drivers/spi/spi-microchip-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)