Message ID | 20240516090430.493122-1-xiao.w.wang@intel.com (mailing list archive) |
---|---|
State | Handled Elsewhere |
Headers | show |
Series | [v3] riscv, bpf: Optimize zextw insn with Zba extension | expand |
On Thu, May 16, 2024 at 05:04:30PM GMT, Xiao Wang wrote: > The Zba extension provides add.uw insn which can be used to implement > zext.w with rs2 set as ZERO. > > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> > --- > v3: > * Remove the Kconfig dependencies on TOOLCHAIN_HAS_ZBA and > RISCV_ALTERNATIVE. (Andrew) > v2: > * Add Zba description in the Kconfig. (Lehui) > * Reword the Kconfig help message to make it clearer. (Conor) > --- > arch/riscv/Kconfig | 12 ++++++++++++ > arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++ > 2 files changed, 30 insertions(+) > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
On 2024/5/16 17:04, Xiao Wang wrote: > The Zba extension provides add.uw insn which can be used to implement > zext.w with rs2 set as ZERO. > > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> > --- > v3: > * Remove the Kconfig dependencies on TOOLCHAIN_HAS_ZBA and > RISCV_ALTERNATIVE. (Andrew) > v2: > * Add Zba description in the Kconfig. (Lehui) > * Reword the Kconfig help message to make it clearer. (Conor) > --- > arch/riscv/Kconfig | 12 ++++++++++++ > arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++ > 2 files changed, 30 insertions(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 6bec1bce6586..b64d55dc929f 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -601,6 +601,18 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO > def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb) > depends on AS_HAS_OPTION_ARCH > > +config RISCV_ISA_ZBA > + bool "Zba extension support for bit manipulation instructions" > + default y > + help > + Add support for enabling optimisations in the kernel when the Zba > + extension is detected at boot. > + > + The Zba extension provides instructions to accelerate the generation > + of addresses that index into arrays of basic data types. > + > + If you don't know what to do here, say Y. > + > config RISCV_ISA_ZBB > bool "Zbb extension support for bit manipulation instructions" > depends on TOOLCHAIN_HAS_ZBB > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h > index f4b6b3b9edda..18a7885ba95e 100644 > --- a/arch/riscv/net/bpf_jit.h > +++ b/arch/riscv/net/bpf_jit.h > @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) > return IS_ENABLED(CONFIG_RISCV_ISA_C); > } > > +static inline bool rvzba_enabled(void) > +{ > + return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA); > +} > + > static inline bool rvzbb_enabled(void) > { > return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); > @@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2) > return rv_css_insn(0x7, imm, rs2, 0x2); > } > > +/* RV64-only ZBA instructions. */ > + > +static inline u32 rvzba_zextw(u8 rd, u8 rs1) > +{ > + /* add.uw rd, rs1, ZERO */ > + return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b); > +} > + > #endif /* __riscv_xlen == 64 */ > > /* Helper functions that emit RVC instructions when possible. */ > @@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx) > > static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx) > { > + if (rvzba_enabled()) { > + emit(rvzba_zextw(rd, rs), ctx); > + return; > + } > + > emit_slli(rd, rs, 32, ctx); > emit_srli(rd, rd, 32, ctx); > } Reviewed-by: Pu Lehui <pulehui@huawei.com> Tested-by: Pu Lehui <pulehui@huawei.com>
Hello: This patch was applied to bpf/bpf-next.git (master) by Daniel Borkmann <daniel@iogearbox.net>: On Thu, 16 May 2024 17:04:30 +0800 you wrote: > The Zba extension provides add.uw insn which can be used to implement > zext.w with rs2 set as ZERO. > > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> > --- > v3: > * Remove the Kconfig dependencies on TOOLCHAIN_HAS_ZBA and > RISCV_ALTERNATIVE. (Andrew) > v2: > * Add Zba description in the Kconfig. (Lehui) > * Reword the Kconfig help message to make it clearer. (Conor) > > [...] Here is the summary with links: - [v3] riscv, bpf: Optimize zextw insn with Zba extension https://git.kernel.org/bpf/bpf-next/c/c12603e76ef6 You are awesome, thank you!
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6bec1bce6586..b64d55dc929f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -601,6 +601,18 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb) depends on AS_HAS_OPTION_ARCH +config RISCV_ISA_ZBA + bool "Zba extension support for bit manipulation instructions" + default y + help + Add support for enabling optimisations in the kernel when the Zba + extension is detected at boot. + + The Zba extension provides instructions to accelerate the generation + of addresses that index into arrays of basic data types. + + If you don't know what to do here, say Y. + config RISCV_ISA_ZBB bool "Zbb extension support for bit manipulation instructions" depends on TOOLCHAIN_HAS_ZBB diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h index f4b6b3b9edda..18a7885ba95e 100644 --- a/arch/riscv/net/bpf_jit.h +++ b/arch/riscv/net/bpf_jit.h @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void) return IS_ENABLED(CONFIG_RISCV_ISA_C); } +static inline bool rvzba_enabled(void) +{ + return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA); +} + static inline bool rvzbb_enabled(void) { return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB); @@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2) return rv_css_insn(0x7, imm, rs2, 0x2); } +/* RV64-only ZBA instructions. */ + +static inline u32 rvzba_zextw(u8 rd, u8 rs1) +{ + /* add.uw rd, rs1, ZERO */ + return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b); +} + #endif /* __riscv_xlen == 64 */ /* Helper functions that emit RVC instructions when possible. */ @@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx) static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx) { + if (rvzba_enabled()) { + emit(rvzba_zextw(rd, rs), ctx); + return; + } + emit_slli(rd, rs, 32, ctx); emit_srli(rd, rd, 32, ctx); }
The Zba extension provides add.uw insn which can be used to implement zext.w with rs2 set as ZERO. Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> --- v3: * Remove the Kconfig dependencies on TOOLCHAIN_HAS_ZBA and RISCV_ALTERNATIVE. (Andrew) v2: * Add Zba description in the Kconfig. (Lehui) * Reword the Kconfig help message to make it clearer. (Conor) --- arch/riscv/Kconfig | 12 ++++++++++++ arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++ 2 files changed, 30 insertions(+)