| Message ID | 20240519050507.2217791-1-xiao.w.wang@intel.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | riscv, bpf: try RVC for reg move within BPF_CMPXCHG JIT | expand |
Xiao Wang <xiao.w.wang@intel.com> writes: > We could try to emit compressed insn for reg move operation during CMPXCHG > JIT, the instruction compression has no impact on the jump offsets of > following forward and backward jump instructions. ...and at some point we should start supporting Zacas and friends, instead of lr/sc. > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> Acked-by: Björn Töpel <bjorn@kernel.org>
Hello: This patch was applied to bpf/bpf-next.git (master) by Daniel Borkmann <daniel@iogearbox.net>: On Sun, 19 May 2024 13:05:07 +0800 you wrote: > We could try to emit compressed insn for reg move operation during CMPXCHG > JIT, the instruction compression has no impact on the jump offsets of > following forward and backward jump instructions. > > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> > --- > arch/riscv/net/bpf_jit_comp64.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) Here is the summary with links: - riscv, bpf: try RVC for reg move within BPF_CMPXCHG JIT https://git.kernel.org/bpf/bpf-next/c/99fa63d9ca60 You are awesome, thank you!
diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c index aac190085472..c134aaec4295 100644 --- a/arch/riscv/net/bpf_jit_comp64.c +++ b/arch/riscv/net/bpf_jit_comp64.c @@ -531,8 +531,10 @@ static void emit_atomic(u8 rd, u8 rs, s16 off, s32 imm, bool is64, /* r0 = atomic_cmpxchg(dst_reg + off16, r0, src_reg); */ case BPF_CMPXCHG: r0 = bpf_to_rv_reg(BPF_REG_0, ctx); - emit(is64 ? rv_addi(RV_REG_T2, r0, 0) : - rv_addiw(RV_REG_T2, r0, 0), ctx); + if (is64) + emit_mv(RV_REG_T2, r0, ctx); + else + emit_addiw(RV_REG_T2, r0, 0, ctx); emit(is64 ? rv_lr_d(r0, 0, rd, 0, 0) : rv_lr_w(r0, 0, rd, 0, 0), ctx); jmp_offset = ninsns_rvoff(8);
We could try to emit compressed insn for reg move operation during CMPXCHG JIT, the instruction compression has no impact on the jump offsets of following forward and backward jump instructions. Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> --- arch/riscv/net/bpf_jit_comp64.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)