diff mbox series

[5/5] riscv: dts: sophgo: Add LicheeRV Nano board device tree

Message ID 20240527-sg2002-v1-5-1b6cb38ce8f4@bootlin.com (mailing list archive)
State Superseded
Headers show
Series Add board support for Sipeed LicheeRV Nano | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-5-test-1 fail .github/scripts/patches/tests/build_rv32_defconfig.sh
conchuod/patch-5-test-2 fail .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh
conchuod/patch-5-test-3 fail .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh
conchuod/patch-5-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-5-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-5-test-6 warning .github/scripts/patches/tests/checkpatch.sh
conchuod/patch-5-test-7 fail .github/scripts/patches/tests/dtb_warn_rv64.sh
conchuod/patch-5-test-8 success .github/scripts/patches/tests/header_inline.sh
conchuod/patch-5-test-9 success .github/scripts/patches/tests/kdoc.sh
conchuod/patch-5-test-10 success .github/scripts/patches/tests/module_param.sh
conchuod/patch-5-test-11 success .github/scripts/patches/tests/verify_fixes.sh
conchuod/patch-5-test-12 success .github/scripts/patches/tests/verify_signedoff.sh

Commit Message

Thomas Bonnefille May 27, 2024, 10:28 a.m. UTC
LicheeRV Nano [1] is an embedded development platform base on the SOPHGO
SG2002 chip.

Add only support for UART.

Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html
[1]

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
 arch/riscv/boot/dts/sophgo/Makefile                |  1 +
 .../boot/dts/sophgo/sg2002-lichee-rv-nano.dts      | 25 ++++++++++++++++++++++
 2 files changed, 26 insertions(+)

Comments

Conor Dooley May 27, 2024, 4:41 p.m. UTC | #1
On Mon, May 27, 2024 at 12:28:21PM +0200, Thomas Bonnefille wrote:
> LicheeRV Nano [1] is an embedded development platform base on the SOPHGO
> SG2002 chip.
> 
> Add only support for UART.
> 
> Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html
> [1]

Just format this as:
Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html [1]
Thomas Bonnefille May 27, 2024, 6:12 p.m. UTC | #2
On 5/27/24 12:28 PM, Thomas Bonnefille wrote:
> LicheeRV Nano [1] is an embedded development platform base on the SOPHGO
> SG2002 chip.
> 
> Add only support for UART.
> 
> Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html
> [1]
> 
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> ---
>   arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>   .../boot/dts/sophgo/sg2002-lichee-rv-nano.dts      | 25 ++++++++++++++++++++++
>   2 files changed, 26 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 57ad82a61ea6..5759b21805dc 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -1,4 +1,5 @@
>   # SPDX-License-Identifier: GPL-2.0
>   dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
>   dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano.dtb
>   dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
>...
> +++ b/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts

I'm really sorry, it seems that I made a mistake here with git, the 
device tree should not have an hyphen in its name, I'll send a new 
version soon to correct this.
Inochi Amaoto May 27, 2024, 10:25 p.m. UTC | #3
On Mon, May 27, 2024 at 12:28:21PM GMT, Thomas Bonnefille wrote:
> LicheeRV Nano [1] is an embedded development platform base on the SOPHGO
> SG2002 chip.
> 
> Add only support for UART.
> 

Although this is OK, I think you can also add sdhci node, it is already
supported.

> Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html
> [1]
> 
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> ---
>  arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>  .../boot/dts/sophgo/sg2002-lichee-rv-nano.dts      | 25 ++++++++++++++++++++++
>  2 files changed, 26 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 57ad82a61ea6..5759b21805dc 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -1,4 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0
>  dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
>  dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano.dtb
>  dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> diff --git a/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts b/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts
> new file mode 100644
> index 000000000000..aaad2733801b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "sg2002.dtsi"
> +
> +/ {
> +	model = "LicheeRV Nano";
> +	compatible = "sipeed,licheerv-nano", "sophgo,sg2002";

Use the right version, rv nano have several versions with different 
peripherals. The compatible is good for the common file, but not the 
specific board.

> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};

It is also better to add all already support nodes, such as gpio, 
other uart port.

> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> 
> -- 
> 2.45.1
>
kernel test robot May 29, 2024, 12:57 a.m. UTC | #4
Hi Thomas,

kernel test robot noticed the following build errors:

[auto build test ERROR on 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0]

url:    https://github.com/intel-lab-lkp/linux/commits/Thomas-Bonnefille/dt-bindings-interrupt-controller-Add-SOPHGO-SG2002-plic/20240527-183235
base:   1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
patch link:    https://lore.kernel.org/r/20240527-sg2002-v1-5-1b6cb38ce8f4%40bootlin.com
patch subject: [PATCH 5/5] riscv: dts: sophgo: Add LicheeRV Nano board device tree
config: riscv-allmodconfig (https://download.01.org/0day-ci/archive/20240529/202405290822.4dIYJxLq-lkp@intel.com/config)
compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project bafda89a0944d947fc4b3b5663185e07a397ac30)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240529/202405290822.4dIYJxLq-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405290822.4dIYJxLq-lkp@intel.com/

All errors (new ones prefixed by >>):

>> make[6]: *** No rule to make target 'arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano.dtb', needed by 'arch/riscv/boot/dts/sophgo/'.
   make[6]: Target 'arch/riscv/boot/dts/sophgo/' not remade because of errors.
Thomas Bonnefille June 10, 2024, 7:30 a.m. UTC | #5
Thank you for your answer :)

On 5/28/24 12:25 AM, Inochi Amaoto wrote:

>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
> 
> It is also better to add all already support nodes, such as gpio,
> other uart port.

I'm importing, cv18xx.dtsi through sg2002.dtsi, so GPIOs are already 
configured and activated by default.
For the other peripherals, all of them are, with the default pinctrl, 
set to function that haven't any driver yet (ADC, MIPI, PWM...).

Based on what I just said, I'm not sure to understand what you mean, can 
you be more specific about the changes you want?
Inochi Amaoto June 10, 2024, 7:38 a.m. UTC | #6
On Mon, Jun 10, 2024 at 09:30:55AM GMT, Thomas Bonnefille wrote:
> Thank you for your answer :)
> 
> On 5/28/24 12:25 AM, Inochi Amaoto wrote:
> 
> > > +
> > > +	aliases {
> > > +		serial0 = &uart0;
> > > +	};
> > > +
> > > +	chosen {
> > > +		stdout-path = "serial0:115200n8";
> > > +	};
> > 
> > It is also better to add all already support nodes, such as gpio,
> > other uart port.
> 
> I'm importing, cv18xx.dtsi through sg2002.dtsi, so GPIOs are already
> configured and activated by default.
> For the other peripherals, all of them are, with the default pinctrl, set to
> function that haven't any driver yet (ADC, MIPI, PWM...).
> 

You forgot sdhci, which is already support the SD.

> Based on what I just said, I'm not sure to understand what you mean, can you
> be more specific about the changes you want?

I suggest adding aliases for all gpio and uart node. You can check 
cv1800b-milkv-duo.dts as an example.
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
index 57ad82a61ea6..5759b21805dc 100644
--- a/arch/riscv/boot/dts/sophgo/Makefile
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -1,4 +1,5 @@ 
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
 dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
+dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano.dtb
 dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
diff --git a/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts b/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts
new file mode 100644
index 000000000000..aaad2733801b
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2002-lichee-rv-nano.dts
@@ -0,0 +1,25 @@ 
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
+ */
+
+/dts-v1/;
+
+#include "sg2002.dtsi"
+
+/ {
+	model = "LicheeRV Nano";
+	compatible = "sipeed,licheerv-nano", "sophgo,sg2002";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};