| Message ID | 20240609-xtheadvector-v1-3-3fe591d7f109@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: Add support for xtheadvector | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On 10 Jun 2024, at 05:45, Charlie Jenkins <charlie@rivosinc.com> wrote: > > The D1/D1s SoCs support xtheadvector so it can be included in the > devicetree. Also include vlenb for the cpu. > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 64c3c2e6cbe0..50c9f4ec8a7f 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -27,7 +27,8 @@ cpu0: cpu@0 { > riscv,isa = "rv64imafdc"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > - "zifencei", "zihpm"; > + "zifencei", "zihpm", "xtheadvector"; > + riscv,vlenb = <128>; thread,vlenb Jess > #cooling-cells = <2>; > > cpu0_intc: interrupt-controller { > > -- > 2.44.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Mon, Jun 10, 2024 at 06:49:30PM +0100, Jessica Clarke wrote: > On 10 Jun 2024, at 05:45, Charlie Jenkins <charlie@rivosinc.com> wrote: > > > > The D1/D1s SoCs support xtheadvector so it can be included in the > > devicetree. Also include vlenb for the cpu. > > > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> > > --- > > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > index 64c3c2e6cbe0..50c9f4ec8a7f 100644 > > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > @@ -27,7 +27,8 @@ cpu0: cpu@0 { > > riscv,isa = "rv64imafdc"; > > riscv,isa-base = "rv64i"; > > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > > - "zifencei", "zihpm"; > > + "zifencei", "zihpm", "xtheadvector"; > > + riscv,vlenb = <128>; > > thread,vlenb Oh right, thank you! - Charlie > > Jess > > > #cooling-cells = <2>; > > > > cpu0_intc: interrupt-controller { > > > > -- > > 2.44.0 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv >
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..50c9f4ec8a7f 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,8 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadvector"; + riscv,vlenb = <128>; #cooling-cells = <2>; cpu0_intc: interrupt-controller {
The D1/D1s SoCs support xtheadvector so it can be included in the devicetree. Also include vlenb for the cpu. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)