| Message ID | 20240612112213.2734748-2-daire.mcnamara@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Fix address translations on MPFS PCIe controller | expand |
On Wed, 12 Jun 2024, daire.mcnamara@microchip.com wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of > three general-purpose Fabric Interface Controller (FIC) buses that > encapsulate an AXI-M interface. That FIC is responsible for managing > the translations of the upper 32-bits of the AXI-M address. On MPFS, > the Root Port driver needs to take account of that outbound address > translation done by the parent FIC bus before setting up its own > outbound address translation tables. In all cases on MPFS, > the remaining outbound address translation tables are 32-bit only. > > Limit the outbound address translation tables to 32-bit only. > > Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Don't leave spaces between tag lines. > --- > drivers/pci/controller/pcie-microchip-host.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c > index 137fb8570ba2..853adce24492 100644 > --- a/drivers/pci/controller/pcie-microchip-host.c > +++ b/drivers/pci/controller/pcie-microchip-host.c > @@ -933,7 +933,7 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port) > > static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, > phys_addr_t axi_addr, phys_addr_t pci_addr, > - size_t size) > + u64 size) I don't see how this is related to what is described by the commit message. If there's need for this change it should be justified properly and it looks to me that resource_size_t would be more appropriate here given the callers use resource_size() to determine this parameter? > { > u32 atr_sz = ilog2(size) - 1; > u32 val; > @@ -983,7 +983,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, > if (resource_type(entry->res) == IORESOURCE_MEM) { > pci_addr = entry->res->start - entry->offset; > mc_pcie_setup_window(bridge_base_addr, index, > - entry->res->start, pci_addr, > + entry->res->start & 0xffffffff, > + pci_addr, > resource_size(entry->res)); > index++; > } > @@ -1117,9 +1118,8 @@ static int mc_platform_init(struct pci_config_window *cfg) > int ret; > > /* Configure address translation table 0 for PCIe config space */ > - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, > - cfg->res.start, > - resource_size(&cfg->res)); > + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, > + 0, resource_size(&cfg->res)); Given your commit message, it would be more obvious to the code reader if the literal is replaced with something like RP_OUTBOUND_TRANS_TBL_MASK (that is GENMASK(31, 0)). Feel free to come up better name if I didn't understand all the details right based on your commit message.
diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 137fb8570ba2..853adce24492 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -933,7 +933,7 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port) static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size) + u64 size) { u32 atr_sz = ilog2(size) - 1; u32 val; @@ -983,7 +983,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, if (resource_type(entry->res) == IORESOURCE_MEM) { pci_addr = entry->res->start - entry->offset; mc_pcie_setup_window(bridge_base_addr, index, - entry->res->start, pci_addr, + entry->res->start & 0xffffffff, + pci_addr, resource_size(entry->res)); index++; } @@ -1117,9 +1118,8 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, + 0, resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win);