| Message ID | 20240628115923.4133286-2-daire.mcnamara@microchip.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Fix address translations on MPFS PCIe controller | expand |
On Fri, 28 Jun 2024, daire.mcnamara@microchip.com wrote: > From: Daire McNamara <daire.mcnamara@microchip.com> > > On Microchip PolarFire SoC (MPFS) the PCIe Root Port can be behind one of > three general-purpose Fabric Interface Controller (FIC) buses that > encapsulate an AXI-M interface. That FIC is responsible for managing > the translations of the upper 32-bits of the AXI-M address. On MPFS, > the Root Port driver needs to take account of that outbound address > translation done by the parent FIC bus before setting up its own > outbound address translation tables. In all cases on MPFS, > the remaining outbound address translation tables are 32-bit only. > > Limit the outbound address translation tables to 32-bit only. > > This necessitates changing a size_t in mc_pcie_setup_window > to a resource_size_t to avoid a compile error on 32-bit platforms. Do you really mean "a compile error" here, that is, building 32-bit kernel fails during compile stage? If not, it would be good to rephrase this line. Other than that, Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> -- i. > Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip Polarfire PCIe controller driver") > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > drivers/pci/controller/pcie-microchip-host.c | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c > index 137fb8570ba2..47c397ae515a 100644 > --- a/drivers/pci/controller/pcie-microchip-host.c > +++ b/drivers/pci/controller/pcie-microchip-host.c > @@ -23,6 +23,8 @@ > /* Number of MSI IRQs */ > #define MC_MAX_NUM_MSI_IRQS 32 > > +#define MC_OUTBOUND_TRANS_TBL_MASK GENMASK(31, 0) > + > /* PCIe Bridge Phy and Controller Phy offsets */ > #define MC_PCIE1_BRIDGE_ADDR 0x00008000u > #define MC_PCIE1_CTRL_ADDR 0x0000a000u > @@ -933,7 +935,7 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port) > > static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, > phys_addr_t axi_addr, phys_addr_t pci_addr, > - size_t size) > + resource_size_t size) > { > u32 atr_sz = ilog2(size) - 1; > u32 val; > @@ -983,7 +985,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, > if (resource_type(entry->res) == IORESOURCE_MEM) { > pci_addr = entry->res->start - entry->offset; > mc_pcie_setup_window(bridge_base_addr, index, > - entry->res->start, pci_addr, > + entry->res->start & MC_OUTBOUND_TRANS_TBL_MASK, > + pci_addr, > resource_size(entry->res)); > index++; > } > @@ -1117,9 +1120,8 @@ static int mc_platform_init(struct pci_config_window *cfg) > int ret; > > /* Configure address translation table 0 for PCIe config space */ > - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, > - cfg->res.start, > - resource_size(&cfg->res)); > + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & MC_OUTBOUND_TRANS_TBL_MASK, > + 0, resource_size(&cfg->res)); > > /* Need some fixups in config space */ > mc_pcie_enable_msi(port, cfg->win);
diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c index 137fb8570ba2..47c397ae515a 100644 --- a/drivers/pci/controller/pcie-microchip-host.c +++ b/drivers/pci/controller/pcie-microchip-host.c @@ -23,6 +23,8 @@ /* Number of MSI IRQs */ #define MC_MAX_NUM_MSI_IRQS 32 +#define MC_OUTBOUND_TRANS_TBL_MASK GENMASK(31, 0) + /* PCIe Bridge Phy and Controller Phy offsets */ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u #define MC_PCIE1_CTRL_ADDR 0x0000a000u @@ -933,7 +935,7 @@ static int mc_pcie_init_irq_domains(struct mc_pcie *port) static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, - size_t size) + resource_size_t size) { u32 atr_sz = ilog2(size) - 1; u32 val; @@ -983,7 +985,8 @@ static int mc_pcie_setup_windows(struct platform_device *pdev, if (resource_type(entry->res) == IORESOURCE_MEM) { pci_addr = entry->res->start - entry->offset; mc_pcie_setup_window(bridge_base_addr, index, - entry->res->start, pci_addr, + entry->res->start & MC_OUTBOUND_TRANS_TBL_MASK, + pci_addr, resource_size(entry->res)); index++; } @@ -1117,9 +1120,8 @@ static int mc_platform_init(struct pci_config_window *cfg) int ret; /* Configure address translation table 0 for PCIe config space */ - mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, - cfg->res.start, - resource_size(&cfg->res)); + mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & MC_OUTBOUND_TRANS_TBL_MASK, + 0, resource_size(&cfg->res)); /* Need some fixups in config space */ mc_pcie_enable_msi(port, cfg->win);