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[3/3] riscv: dts: sophgo: Add SARADC configuration

Message ID 20240702-sg2002-adc-v1-3-ac66e076a756@bootlin.com (mailing list archive)
State Handled Elsewhere
Headers show
Series Add SARADC support on Sophgo SoC | expand

Commit Message

Thomas Bonnefille July 2, 2024, 11:52 a.m. UTC
Adds SARADC nodes for the common Successive Approximation Analog to
Digital Converter used in Sophgo SoC.
This patch adds nodes for the two SARADCs presents on the board, one in
the Active domain and the other in the No-Die domain.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Krzysztof Kozlowski July 3, 2024, 5:09 a.m. UTC | #1
On 02/07/2024 13:52, Thomas Bonnefille wrote:
> Adds SARADC nodes for the common Successive Approximation Analog to
> Digital Converter used in Sophgo SoC.
> This patch adds nodes for the two SARADCs presents on the board, one in
> the Active domain and the other in the No-Die domain.

You are duplicating the first sentence or this does not make sense...

> 
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> ---
>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index 7247c7c3013c..0b996aa7fa31 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -309,5 +309,19 @@ clint: timer@74000000 {
>  			reg = <0x74000000 0x10000>;
>  			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
>  		};
> +
> +		saradc_active: adc@30f0000 {

Please look at DTS coding style about ordering of nodes.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 7247c7c3013c..0b996aa7fa31 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -309,5 +309,19 @@  clint: timer@74000000 {
 			reg = <0x74000000 0x10000>;
 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
 		};
+
+		saradc_active: adc@30f0000 {
+			compatible = "sophgo,cv18xx-saradc";
+			clocks = <&clk CLK_SARADC>;
+			interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x030F0000 0x1000>;
+			status = "disabled";
+		};
+
+		saradc_nodie: adc@502c000 {
+			compatible = "sophgo,cv18xx-saradc";
+			reg = <0x0502C000 0x1000>;
+			status = "disabled";
+		};
 	};
 };