[GIT,PULL] RISC-V cache drivers for v6.11

Message ID	20240707-whoever-undesired-c5f6e96ae403@spud (mailing list archive)
State	Handled Elsewhere
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> Date: Sun, 7 Jul 2024 18:27:42 +0100 From: Conor Dooley <conor@kernel.org> To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V cache drivers for v6.11 Message-ID: <20240707-whoever-undesired-c5f6e96ae403@spud> MIME-Version: 1.0 Precedence: list Content-Type: multipart/mixed; boundary="===============4772597711155964699==" Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	[GIT,PULL] RISC-V cache drivers for v6.11 \| expand [GIT,PULL] RISC-V cache drivers for v6.11

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20240707-whoever-undesired-c5f6e96ae403@spud (mailing list archive)

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Handled Elsewhere

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Date: Sun, 7 Jul 2024 18:27:42 +0100
From: Conor Dooley <conor@kernel.org>
To: soc@kernel.org
Cc: conor@kernel.org, linux-riscv@lists.infradead.org
Subject: [GIT PULL] RISC-V cache drivers for v6.11
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[GIT,PULL] RISC-V cache drivers for v6.11 | expand

Context	Check	Description
conchuod/vmtest-fixes-PR	fail	merge-conflict

Context

Check

Description

conchuod/vmtest-fixes-PR

fail

merge-conflict

Message

Conor Dooley July 7, 2024, 5:27 p.m. UTC

Hey Arnd,

Another attempt 2 with a fixed $subject.

Please pull the addition of a new cache driver.

There's a wee maintainers update in here too, I put the series on this
branch as one patch is cache related and I have no soc driver patches.

Cheers,
Conor.

The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0:

  Linux 6.10-rc1 (2024-05-26 15:20:12 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-cache-for-v6.11

for you to fetch changes up to 3d41249c1dee0fa22ebd8d27aa0a280edf943a0e:

  MAINTAINERS: add microchip soc binding directory to microchip soc driver entry (2024-06-27 17:33:06 +0100)

----------------------------------------------------------------
RISC-V cache drivers for v6.11

StarFive:
A new driver for the cache controller on the jh8100, which didn't
implement Zicbom and thus needs an implementation of non-standard cache
management operations.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

----------------------------------------------------------------
Conor Dooley (2):
      MAINTAINERS: add cache binding directory to cache driver entry
      MAINTAINERS: add microchip soc binding directory to microchip soc driver entry

Joshua Yeong (2):
      dt-bindings: cache: Add docs for StarFive Starlink cache controller
      cache: Add StarFive StarLink cache management

 .../cache/starfive,jh8100-starlink-cache.yaml      |  66 +++++++++++
 MAINTAINERS                                        |   2 +
 drivers/cache/Kconfig                              |   9 ++
 drivers/cache/Makefile                             |   5 +-
 drivers/cache/starfive_starlink_cache.c            | 130 +++++++++++++++++++++
 5 files changed, 210 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
 create mode 100644 drivers/cache/starfive_starlink_cache.c

[GIT,PULL] RISC-V cache drivers for v6.11

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