[GIT,PULL] RISC-V soc fixes for v6.11-final

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Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> Date: Mon, 9 Sep 2024 15:33:36 +0100 From: Conor Dooley <conor@kernel.org> To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V soc fixes for v6.11-final Message-ID: <20240909-hybrid-groovy-601a33b5b309@spud> MIME-Version: 1.0 Precedence: list Content-Type: multipart/mixed; boundary="===============2423356840127917147==" Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	[GIT,PULL] RISC-V soc fixes for v6.11-final \| expand [GIT,PULL] RISC-V soc fixes for v6.11-final

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20240909-hybrid-groovy-601a33b5b309@spud (mailing list archive)

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Date: Mon, 9 Sep 2024 15:33:36 +0100
From: Conor Dooley <conor@kernel.org>
To: soc@kernel.org
Cc: conor@kernel.org, linux-riscv@lists.infradead.org
Subject: [GIT PULL] RISC-V soc fixes for v6.11-final
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[GIT,PULL] RISC-V soc fixes for v6.11-final | expand

Context	Check	Description
conchuod/vmtest-fixes-PR	fail	merge-conflict

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Description

conchuod/vmtest-fixes-PR

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Conor Dooley Sept. 9, 2024, 2:33 p.m. UTC

Hey Arnd,

Here's the fix that was being discussed on IRC over the weekend.

Cheers,
conor.

The following changes since commit 591940e22e287fb64ac07be275e343d860cb72d6:

  firmware: microchip: fix incorrect error report of programming:timeout on success (2024-08-22 20:47:16 +0100)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/riscv-soc-fixes-for-v6.11-final

for you to fetch changes up to 61f2e8a3a94175dbbaad6a54f381b2a505324610:

  riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz (2024-09-08 23:20:19 +0100)

----------------------------------------------------------------
RISC-V soc fixes for v6.11-final

StarFive:
A fix to return one of the clocks on the JH7110 from 1 GHz to 1.5 GHz

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

----------------------------------------------------------------
Xingyu Wu (1):
      riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz

 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

[GIT,PULL] RISC-V soc fixes for v6.11-final

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