[GIT,PULL] RISC-V config for v6.12

Message ID	20240910-annex-ravage-07d63041a7c5@spud (mailing list archive)
State	Handled Elsewhere
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> Date: Tue, 10 Sep 2024 23:02:17 +0100 From: Conor Dooley <conor@kernel.org> To: soc@kernel.org Cc: conor@kernel.org, palmer@dabbelt.com, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V config for v6.12 Message-ID: <20240910-annex-ravage-07d63041a7c5@spud> MIME-Version: 1.0 Precedence: list Content-Type: multipart/mixed; boundary="===============2535931206423146765==" Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	[GIT,PULL] RISC-V config for v6.12 \| expand [GIT,PULL] RISC-V config for v6.12

Message ID

20240910-annex-ravage-07d63041a7c5@spud (mailing list archive)

State

Handled Elsewhere

Headers

Date: Tue, 10 Sep 2024 23:02:17 +0100
From: Conor Dooley <conor@kernel.org>
To: soc@kernel.org
Cc: conor@kernel.org, palmer@dabbelt.com, linux-riscv@lists.infradead.org
Subject: [GIT PULL] RISC-V config for v6.12
Message-ID: <20240910-annex-ravage-07d63041a7c5@spud>
MIME-Version: 1.0
Precedence: list
Content-Type: multipart/mixed; boundary="===============2535931206423146765=="
Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Errors-To: 
 linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org

Series

[GIT,PULL] RISC-V config for v6.12 | expand

Context	Check	Description
conchuod/vmtest-fixes-PR	fail	merge-conflict

Context

Check

Description

conchuod/vmtest-fixes-PR

fail

merge-conflict

Message

Conor Dooley Sept. 10, 2024, 10:02 p.m. UTC

Hey Arnd,

Practically nothing for you this cycle, so this will be my only PR.
There's both Microchip and Spacemit stuff on the lists, but none of it
ready for this cycle.

Cheers,
Conor.

The following changes since commit 8400291e289ee6b2bf9779ff1c83a291501f017b:

  Linux 6.11-rc1 (2024-07-28 14:19:55 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-config-for-v6.12

for you to fetch changes up to 72160ec6cb12613663f26d89049b95f8dc9fa000:

  riscv: defconfig: Enable pinctrl support for CV18XX Series SoC (2024-09-09 12:55:53 +0100)

----------------------------------------------------------------
RISC-V config for v6.12

Two patches, enabling clock and pinctrl support in defconfig for Sopghgo
devices.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

----------------------------------------------------------------
Chen Wang (1):
      riscv: defconfig: sophgo: enable clks for sg2042

Inochi Amaoto (1):
      riscv: defconfig: Enable pinctrl support for CV18XX Series SoC

 arch/riscv/configs/defconfig | 7 +++++++
 1 file changed, 7 insertions(+)

[GIT,PULL] RISC-V config for v6.12

Pull-request

Checks

Message