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[v10,06/14] RISC-V: define the elements of the VCSR vector CSR

Message ID 20240911-xtheadvector-v10-6-8d3930091246@rivosinc.com (mailing list archive)
State New
Headers show
Series riscv: Add support for xtheadvector | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-6-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh took 130.56s
conchuod/patch-6-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh took 1959.00s
conchuod/patch-6-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh took 2199.30s
conchuod/patch-6-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh took 19.80s
conchuod/patch-6-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh took 21.67s
conchuod/patch-6-test-6 warning .github/scripts/patches/tests/checkpatch.sh took 0.43s
conchuod/patch-6-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh took 41.82s
conchuod/patch-6-test-8 success .github/scripts/patches/tests/header_inline.sh took 0.01s
conchuod/patch-6-test-9 success .github/scripts/patches/tests/kdoc.sh took 0.56s
conchuod/patch-6-test-10 success .github/scripts/patches/tests/module_param.sh took 0.01s
conchuod/patch-6-test-11 success .github/scripts/patches/tests/verify_fixes.sh took 0.00s
conchuod/patch-6-test-12 success .github/scripts/patches/tests/verify_signedoff.sh took 0.03s

Commit Message

Charlie Jenkins Sept. 12, 2024, 5:55 a.m. UTC
From: Heiko Stuebner <heiko@sntech.de>

The VCSR CSR contains two elements VXRM[2:1] and VXSAT[0].

Define constants for those to access the elements in a readable way.

Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
 arch/riscv/include/asm/csr.h | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 25966995da04..3eeb07d73065 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -300,6 +300,10 @@ 
 #define CSR_STIMECMP		0x14D
 #define CSR_STIMECMPH		0x15D
 
+#define VCSR_VXRM_MASK			3
+#define VCSR_VXRM_SHIFT			1
+#define VCSR_VXSAT_MASK			1
+
 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
 #define CSR_SISELECT		0x150
 #define CSR_SIREG		0x151