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[v10,07/14] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT

Message ID 20240911-xtheadvector-v10-7-8d3930091246@rivosinc.com (mailing list archive)
State New
Headers show
Series riscv: Add support for xtheadvector | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-7-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh took 127.18s
conchuod/patch-7-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh took 1956.77s
conchuod/patch-7-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh took 2193.41s
conchuod/patch-7-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh took 19.80s
conchuod/patch-7-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh took 21.70s
conchuod/patch-7-test-6 success .github/scripts/patches/tests/checkpatch.sh took 0.42s
conchuod/patch-7-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh took 42.13s
conchuod/patch-7-test-8 success .github/scripts/patches/tests/header_inline.sh took 0.01s
conchuod/patch-7-test-9 success .github/scripts/patches/tests/kdoc.sh took 0.55s
conchuod/patch-7-test-10 success .github/scripts/patches/tests/module_param.sh took 0.01s
conchuod/patch-7-test-11 success .github/scripts/patches/tests/verify_fixes.sh took 0.00s
conchuod/patch-7-test-12 success .github/scripts/patches/tests/verify_signedoff.sh took 0.03s

Commit Message

Charlie Jenkins Sept. 12, 2024, 5:55 a.m. UTC
The VXRM vector csr for xtheadvector has an encoding of 0xa and VXSAT
has an encoding of 0x9.

Co-developed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
 arch/riscv/include/asm/csr.h | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 3eeb07d73065..c0a60c4ed911 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -300,9 +300,14 @@ 
 #define CSR_STIMECMP		0x14D
 #define CSR_STIMECMPH		0x15D
 
-#define VCSR_VXRM_MASK			3
-#define VCSR_VXRM_SHIFT			1
-#define VCSR_VXSAT_MASK			1
+/* xtheadvector symbolic CSR names */
+#define CSR_VXSAT		0x9
+#define CSR_VXRM		0xa
+
+/* xtheadvector CSR masks */
+#define CSR_VXRM_MASK		3
+#define CSR_VXRM_SHIFT		1
+#define CSR_VXSAT_MASK		1
 
 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
 #define CSR_SISELECT		0x150