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[v2] riscv: add Siflower RISC-V SoC family Kconfig support

Message ID 20250120022359.125952-1-gch981213@gmail.com (mailing list archive)
State New
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Series [v2] riscv: add Siflower RISC-V SoC family Kconfig support | expand

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Context Check Description
conchuod/vmtest-for-next-PR success PR summary
conchuod/patch-1-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh took 103.68s
conchuod/patch-1-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh took 1017.91s
conchuod/patch-1-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh took 1197.41s
conchuod/patch-1-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh took 16.14s
conchuod/patch-1-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh took 17.57s
conchuod/patch-1-test-6 warning .github/scripts/patches/tests/checkpatch.sh took 0.36s
conchuod/patch-1-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh took 35.94s
conchuod/patch-1-test-8 success .github/scripts/patches/tests/header_inline.sh took 0.00s
conchuod/patch-1-test-9 success .github/scripts/patches/tests/kdoc.sh took 0.47s
conchuod/patch-1-test-10 success .github/scripts/patches/tests/module_param.sh took 0.01s
conchuod/patch-1-test-11 success .github/scripts/patches/tests/verify_fixes.sh took 0.00s
conchuod/patch-1-test-12 success .github/scripts/patches/tests/verify_signedoff.sh took 0.02s

Commit Message

Chuanhong Guo Jan. 20, 2025, 2:23 a.m. UTC
Siflower RISC-V SoCs, including SF21A6826, SF21H8898 and some other
upcomping chips, are RISC-V chips with T-Head C908 cores for home
routers and gateways. Add a Kconfig entry named ARCH_SIFLOWER for
them.
Notably these chips uses ARM PL011 for UART. ARM_AMBA is selected
for its driver.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
---

Changes since v1:
 * removed deprecated SOC_ symbol

 arch/riscv/Kconfig.socs | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Conor Dooley Jan. 20, 2025, 6:48 p.m. UTC | #1
On Mon, Jan 20, 2025 at 10:23:58AM +0800, Chuanhong Guo wrote:
> Siflower RISC-V SoCs, including SF21A6826, SF21H8898 and some other
> upcomping chips, are RISC-V chips with T-Head C908 cores for home
> routers and gateways. Add a Kconfig entry named ARCH_SIFLOWER for
> them.
> Notably these chips uses ARM PL011 for UART. ARM_AMBA is selected
> for its driver.
> 
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>

This needs to be in a series with the user (your dts)

> ---
> 
> Changes since v1:
>  * removed deprecated SOC_ symbol
> 
>  arch/riscv/Kconfig.socs | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 1916cf7ba450..64a49e7ea03e 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -19,6 +19,12 @@ config ARCH_SIFIVE
>  	help
>  	  This enables support for SiFive SoC platform hardware.
>  
> +config ARCH_SIFLOWER
> +	bool "Siflower RISC-V SoCs"
> +	select ARM_AMBA if TTY
> +	help
> +	  This enables support for Siflower RISC-V SoC platform hardware.
> +
>  config ARCH_SOPHGO
>  	bool "Sophgo SoCs"
>  	help
> -- 
> 2.48.1
> 
>
Chuanhong Guo Jan. 21, 2025, 1:04 a.m. UTC | #2
Hello!

On Tue, Jan 21, 2025 at 2:48 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Mon, Jan 20, 2025 at 10:23:58AM +0800, Chuanhong Guo wrote:
> > Siflower RISC-V SoCs, including SF21A6826, SF21H8898 and some other
> > upcomping chips, are RISC-V chips with T-Head C908 cores for home
> > routers and gateways. Add a Kconfig entry named ARCH_SIFLOWER for
> > them.
> > Notably these chips uses ARM PL011 for UART. ARM_AMBA is selected
> > for its driver.
> >
> > Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
>
> This needs to be in a series with the user (your dts)

Could the user be a driver Kconfig instead? When submitting a GPIO driver I
was suggested to not depend on architecture symbol and add soc-specific
ones to arch/ first. [0]

I still need to polish the clock/reset driver a bit before submitting them.
Without a clock driver I can't really submit a dts with meaningful content.

[0] https://lore.kernel.org/linux-gpio/CACRpkdYi_+aQ5L-c4=w9MK-6Uh0e9dX0nnU6LcZcHd90j97q7w@mail.gmail.com/T/#mf2352fb36ed2cb8c6574d9eb0d4c261d9346bf10
Conor Dooley Jan. 21, 2025, 1:10 a.m. UTC | #3
On Tue, Jan 21, 2025 at 09:04:47AM +0800, Chuanhong Guo wrote:
> Hello!
> 
> On Tue, Jan 21, 2025 at 2:48 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Mon, Jan 20, 2025 at 10:23:58AM +0800, Chuanhong Guo wrote:
> > > Siflower RISC-V SoCs, including SF21A6826, SF21H8898 and some other
> > > upcomping chips, are RISC-V chips with T-Head C908 cores for home
> > > routers and gateways. Add a Kconfig entry named ARCH_SIFLOWER for
> > > them.
> > > Notably these chips uses ARM PL011 for UART. ARM_AMBA is selected
> > > for its driver.
> > >
> > > Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
> >
> > This needs to be in a series with the user (your dts)
> 
> Could the user be a driver Kconfig instead? When submitting a GPIO driver I
> was suggested to not depend on architecture symbol and add soc-specific
> ones to arch/ first. [0]
> 
> I still need to polish the clock/reset driver a bit before submitting them.
> Without a clock driver I can't really submit a dts with meaningful content.
> 
> [0] https://lore.kernel.org/linux-gpio/CACRpkdYi_+aQ5L-c4=w9MK-6Uh0e9dX0nnU6LcZcHd90j97q7w@mail.gmail.com/T/#mf2352fb36ed2cb8c6574d9eb0d4c261d9346bf10

Send it with the GPIO driver then please.
diff mbox series

Patch

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1916cf7ba450..64a49e7ea03e 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -19,6 +19,12 @@  config ARCH_SIFIVE
 	help
 	  This enables support for SiFive SoC platform hardware.
 
+config ARCH_SIFLOWER
+	bool "Siflower RISC-V SoCs"
+	select ARM_AMBA if TTY
+	help
+	  This enables support for Siflower RISC-V SoC platform hardware.
+
 config ARCH_SOPHGO
 	bool "Sophgo SoCs"
 	help