@@ -23,6 +23,8 @@
/* MMC timing mode switch bit */
#define CCU_MMC_NEW_TIMING_MODE BIT(30)
+#define CCU_KEY_VALUE 0x16aa0000
+
struct device_node;
struct ccu_common {
@@ -20,6 +20,9 @@ void ccu_gate_helper_disable(struct ccu_common *common, u32 gate)
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
+ if (common->features & CCU_FEATURE_KEY_FIELD)
+ reg |= CCU_KEY_VALUE;
+
writel(reg & ~gate, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
@@ -44,6 +47,9 @@ int ccu_gate_helper_enable(struct ccu_common *common, u32 gate)
spin_lock_irqsave(common->lock, flags);
reg = readl(common->base + common->reg);
+ if (common->features & CCU_FEATURE_KEY_FIELD)
+ reg |= CCU_KEY_VALUE;
+
writel(reg | gate, common->base + common->reg);
spin_unlock_irqrestore(common->lock, flags);
@@ -68,6 +68,20 @@ struct ccu_gate {
} \
}
+#define SUNXI_CCU_GATE_HWS_WITH_KEY(_struct, _name, _parent, _reg, \
+ _gate, _flags) \
+ struct ccu_gate _struct = { \
+ .enable = _gate, \
+ .common = { \
+ .reg = _reg, \
+ .features = CCU_FEATURE_KEY_FIELD, \
+ .hw.init = CLK_HW_INIT_HWS(_name, \
+ _parent, \
+ &ccu_gate_ops, \
+ _flags), \
+ } \
+ }
+
#define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \
_gate, _prediv, _flags) \
struct ccu_gate _struct = { \
@@ -12,8 +12,6 @@
#include "ccu_gate.h"
#include "ccu_mux.h"
-#define CCU_MUX_KEY_VALUE 0x16aa0000
-
static u16 ccu_mux_get_prediv(struct ccu_common *common,
struct ccu_mux_internal *cm,
int parent_index)
@@ -196,7 +194,7 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
/* The key field always reads as zero. */
if (common->features & CCU_FEATURE_KEY_FIELD)
- reg |= CCU_MUX_KEY_VALUE;
+ reg |= CCU_KEY_VALUE;
reg &= ~GENMASK(cm->width + cm->shift - 1, cm->shift);
writel(reg | (index << cm->shift), common->base + common->reg);
@@ -9,6 +9,7 @@
#include <linux/reset-controller.h>
#include "ccu_reset.h"
+#include "ccu_common.h"
static int ccu_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
@@ -21,6 +22,9 @@ static int ccu_reset_assert(struct reset_controller_dev *rcdev,
spin_lock_irqsave(ccu->lock, flags);
reg = readl(ccu->base + map->reg);
+ if (map->features & CCU_FEATURE_KEY_FIELD)
+ reg |= CCU_KEY_VALUE;
+
writel(reg & ~map->bit, ccu->base + map->reg);
spin_unlock_irqrestore(ccu->lock, flags);
@@ -39,6 +43,9 @@ static int ccu_reset_deassert(struct reset_controller_dev *rcdev,
spin_lock_irqsave(ccu->lock, flags);
reg = readl(ccu->base + map->reg);
+ if (map->features & CCU_FEATURE_KEY_FIELD)
+ reg |= CCU_KEY_VALUE;
+
writel(reg | map->bit, ccu->base + map->reg);
spin_unlock_irqrestore(ccu->lock, flags);
@@ -12,9 +12,9 @@
struct ccu_reset_map {
u16 reg;
u32 bit;
+ u32 features;
};
-
struct ccu_reset {
void __iomem *base;
const struct ccu_reset_map *reset_map;
Some newer SoCs, like V853 has reset and gate registers, what can be write only with fixed key value. Move this value from ccu_mux and reuse in the reset code, and also introduce a new macro to support writing gate registers with a key. Signed-off-by: Andras Szemzo <szemzo.andras@gmail.com> --- drivers/clk/sunxi-ng/ccu_common.h | 2 ++ drivers/clk/sunxi-ng/ccu_gate.c | 6 ++++++ drivers/clk/sunxi-ng/ccu_gate.h | 14 ++++++++++++++ drivers/clk/sunxi-ng/ccu_mux.c | 4 +--- drivers/clk/sunxi-ng/ccu_reset.c | 7 +++++++ drivers/clk/sunxi-ng/ccu_reset.h | 2 +- 6 files changed, 31 insertions(+), 4 deletions(-)