| Message ID | 20250209220646.1090868-4-alexander.sverdlin@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64 support for Milk-V Duo Module 01 EVB | expand |
| Context | Check | Description |
|---|---|---|
| bjorn/pre-ci_am | success | Success |
| bjorn/build-rv32-defconfig | success | build-rv32-defconfig |
| bjorn/build-rv64-clang-allmodconfig | success | build-rv64-clang-allmodconfig |
| bjorn/build-rv64-gcc-allmodconfig | success | build-rv64-gcc-allmodconfig |
| bjorn/build-rv64-nommu-k210-defconfig | success | build-rv64-nommu-k210-defconfig |
| bjorn/build-rv64-nommu-k210-virt | success | build-rv64-nommu-k210-virt |
| bjorn/checkpatch | warning | checkpatch |
| bjorn/dtb-warn-rv64 | success | dtb-warn-rv64 |
| bjorn/header-inline | success | header-inline |
| bjorn/kdoc | success | kdoc |
| bjorn/module-param | success | module-param |
| bjorn/verify-fixes | success | verify-fixes |
| bjorn/verify-signedoff | success | verify-signedoff |
On Sun, Feb 09, 2025 at 11:06:28PM +0100, Alexander Sverdlin wrote: > Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Can you add a riscv version of the this file too? This also applies to patch 4 and 5 Regards, Inochi > --- > arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++ > 1 file changed, 79 insertions(+) > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi > > diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > new file mode 100644 > index 000000000000..4e520486cbe5 > --- /dev/null > +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > @@ -0,0 +1,79 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > + > +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <riscv/sophgo/cv18xx-periph.dtsi> > +#include <riscv/sophgo/cv181x.dtsi> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "sophgo,sg2000"; > + interrupt-parent = <&gic>; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x20000000>; /* 512MiB */ > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0>; > + i-cache-size = <32768>; > + d-cache-size = <32768>; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache { > + compatible = "cache"; > + cache-level= <2>; > + cache-size = <0x20000>; > + }; > + }; > + > + pmu { > + compatible = "arm,cortex-a53-pmu"; > + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; > + always-on; > + clock-frequency = <25000000>; > + }; > + > + gic: interrupt-controller@1f01000 { > + compatible = "arm,cortex-a15-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; > + reg = <0x01f01000 0x1000>, > + <0x01f02000 0x2000>; > + }; > + > + soc { > + ranges; > + > + pinctrl: pinctrl@3001000 { > + compatible = "sophgo,sg2000-pinctrl"; > + reg = <0x03001000 0x1000>, > + <0x05027000 0x1000>; > + reg-names = "sys", "rtc"; > + }; > + }; > +}; > + > + > +&clk { > + compatible = "sophgo,sg2000-clk"; > +}; > -- > 2.48.1 >
On Sun, Feb 09, 2025 at 11:06:28PM +0100, Alexander Sverdlin wrote: > Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> > --- > arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++ > 1 file changed, 79 insertions(+) > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi > > diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > new file mode 100644 > index 000000000000..4e520486cbe5 > --- /dev/null > +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > @@ -0,0 +1,79 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > + > +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <riscv/sophgo/cv18xx-periph.dtsi> > +#include <riscv/sophgo/cv181x.dtsi> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "sophgo,sg2000"; > + interrupt-parent = <&gic>; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x20000000>; /* 512MiB */ > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0>; > + i-cache-size = <32768>; > + d-cache-size = <32768>; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache { > + compatible = "cache"; > + cache-level= <2>; > + cache-size = <0x20000>; > + }; > + }; > + > + pmu { > + compatible = "arm,cortex-a53-pmu"; > + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; > + always-on; > + clock-frequency = <25000000>; > + }; > + > + gic: interrupt-controller@1f01000 { > + compatible = "arm,cortex-a15-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; > + reg = <0x01f01000 0x1000>, > + <0x01f02000 0x2000>; > + }; > + Separate these into a separate CPU file so SG2002 can reuse it. > + soc { > + ranges; > + > + pinctrl: pinctrl@3001000 { > + compatible = "sophgo,sg2000-pinctrl"; > + reg = <0x03001000 0x1000>, > + <0x05027000 0x1000>; > + reg-names = "sys", "rtc"; > + }; > + }; > +}; > + > + > +&clk { > + compatible = "sophgo,sg2000-clk"; > +}; > -- > 2.48.1 >
On 09/02/2025 23:06, Alexander Sverdlin wrote: > Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> > --- > arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++ > 1 file changed, 79 insertions(+) > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi > > diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > new file mode 100644 > index 000000000000..4e520486cbe5 > --- /dev/null > +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > @@ -0,0 +1,79 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > + > +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <riscv/sophgo/cv18xx-periph.dtsi> > +#include <riscv/sophgo/cv181x.dtsi> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "sophgo,sg2000"; > + interrupt-parent = <&gic>; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x20000000>; /* 512MiB */ > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a53"; > + device_type = "cpu"; > + reg = <0>; > + i-cache-size = <32768>; > + d-cache-size = <32768>; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache { > + compatible = "cache"; > + cache-level= <2>; > + cache-size = <0x20000>; > + }; > + }; > + > + pmu { > + compatible = "arm,cortex-a53-pmu"; > + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; > + always-on; > + clock-frequency = <25000000>; > + }; > + > + gic: interrupt-controller@1f01000 { MMIO nodes are always in the soc. > + compatible = "arm,cortex-a15-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; > + reg = <0x01f01000 0x1000>, > + <0x01f02000 0x2000>; > + }; > + > + soc { Override by phandle/label instead of duplicating. > + ranges; > + > + pinctrl: pinctrl@3001000 { > + compatible = "sophgo,sg2000-pinctrl"; > + reg = <0x03001000 0x1000>, > + <0x05027000 0x1000>; > + reg-names = "sys", "rtc"; > + }; > + }; > +}; > + > + > +&clk { > + compatible = "sophgo,sg2000-clk"; That's discouraged practice. If you need to define compatible, it means the block is not shared between designs and must not be in common DTSI. Best regards, Krzysztof
Hi Inochi, On Mon, 2025-02-10 at 13:05 +0800, Inochi Amaoto wrote: > > Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). > > > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> > > Can you add a riscv version of the this file too? This also applies > to patch 4 and 5 this would require binary Sophgo RiscV toolchain, which was the whole point of my ARM64 BSP. So, while I could add RiscV counterparts, they would be completely untested. On the macro level that how I see the current state of upstream affairs: RiscV: There are necessary upstream packages available required to boot, but there is no upstream toolchain to build them. ARM64: There is an upstream toolchain, but the published U-Boot is being linked with ATF binaries -- I was planning to come up with pure U-Boot BSP for this, without binary blobs.
Hi Krzysztof! On Mon, 2025-02-10 at 09:45 +0100, Krzysztof Kozlowski wrote: > On 09/02/2025 23:06, Alexander Sverdlin wrote: > > Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). > > > > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> > > --- > > arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++ > > 1 file changed, 79 insertions(+) > > create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi > > > > diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > > new file mode 100644 > > index 000000000000..4e520486cbe5 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > > @@ -0,0 +1,79 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > + > > +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) > > + > > +#include <dt-bindings/interrupt-controller/arm-gic.h> > > +#include <riscv/sophgo/cv18xx-periph.dtsi> > > +#include <riscv/sophgo/cv181x.dtsi> > > + > > +/ { [...] > > + gic: interrupt-controller@1f01000 { > > MMIO nodes are always in the soc. I think I've looked a wrong example (or a counter-example)... $ grep -R -P '^\t\tcompatible = "arm,cortex-a15-gic";' * arm/boot/dts/intel/axm/axm55xx.dtsi: compatible = "arm,cortex-a15-gic"; arm/boot/dts/ti/omap/dra7.dtsi: compatible = "arm,cortex-a15-gic"; arm/boot/dts/ti/omap/omap5.dtsi: compatible = "arm,cortex-a15-gic"; arm/boot/dts/nvidia/tegra124.dtsi: compatible = "arm,cortex-a15-gic"; arm/boot/dts/nvidia/tegra114.dtsi: compatible = "arm,cortex-a15-gic"; arm64/boot/dts/nvidia/tegra132.dtsi: compatible = "arm,cortex-a15-gic"; arm64/boot/dts/freescale/s32v234.dtsi: compatible = "arm,cortex-a15-gic"; arm64/boot/dts/apm/apm-storm.dtsi: compatible = "arm,cortex-a15-gic"; arm64/boot/dts/apm/apm-shadowcat.dtsi: compatible = "arm,cortex-a15-gic"; But thanks for clarification! > > + compatible = "arm,cortex-a15-gic"; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + reg = <0x01f01000 0x1000>, > > + <0x01f02000 0x2000>; > > + }; > > + > > + soc { > > Override by phandle/label instead of duplicating. > > > + ranges; > > + > > + pinctrl: pinctrl@3001000 { > > + compatible = "sophgo,sg2000-pinctrl"; > > + reg = <0x03001000 0x1000>, > > + <0x05027000 0x1000>; > > + reg-names = "sys", "rtc"; > > + }; > > + }; > > +}; > > + > > + > > +&clk { > > + compatible = "sophgo,sg2000-clk"; > > > That's discouraged practice. If you need to define compatible, it means > the block is not shared between designs and must not be in common DTSI. That doesn't come from my series, that's how original cv18xx.dtsi has been designed. Same question as before: do I need to rework it if I will not be able to test the changes (I don't even posess the relevant HW). But if not, I have to adapt the same pattern into the new sg2000.dtsi.
On 10/02/2025 16:01, Alexander Sverdlin wrote: > Hi Krzysztof! > > On Mon, 2025-02-10 at 09:45 +0100, Krzysztof Kozlowski wrote: >> On 09/02/2025 23:06, Alexander Sverdlin wrote: >>> Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). >>> >>> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> >>> --- >>> arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++ >>> 1 file changed, 79 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi >>> new file mode 100644 >>> index 000000000000..4e520486cbe5 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi >>> @@ -0,0 +1,79 @@ >>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >>> + >>> +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) >>> + >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>> +#include <riscv/sophgo/cv18xx-periph.dtsi> >>> +#include <riscv/sophgo/cv181x.dtsi> >>> + >>> +/ { > > [...] > >>> + gic: interrupt-controller@1f01000 { >> >> MMIO nodes are always in the soc. > > I think I've looked a wrong example (or a counter-example)... > $ grep -R -P '^\t\tcompatible = "arm,cortex-a15-gic";' * > arm/boot/dts/intel/axm/axm55xx.dtsi: compatible = "arm,cortex-a15-gic"; > arm/boot/dts/ti/omap/dra7.dtsi: compatible = "arm,cortex-a15-gic"; > arm/boot/dts/ti/omap/omap5.dtsi: compatible = "arm,cortex-a15-gic"; > arm/boot/dts/nvidia/tegra124.dtsi: compatible = "arm,cortex-a15-gic"; > arm/boot/dts/nvidia/tegra114.dtsi: compatible = "arm,cortex-a15-gic"; These are all old. > arm64/boot/dts/nvidia/tegra132.dtsi: compatible = "arm,cortex-a15-gic"; > arm64/boot/dts/freescale/s32v234.dtsi: compatible = "arm,cortex-a15-gic"; Well, it happens. > arm64/boot/dts/apm/apm-storm.dtsi: compatible = "arm,cortex-a15-gic"; > arm64/boot/dts/apm/apm-shadowcat.dtsi: compatible = "arm,cortex-a15-gic"; These are strong anti-patterns. Unmaintained. > > But thanks for clarification! > >>> + compatible = "arm,cortex-a15-gic"; >>> + interrupt-controller; >>> + #interrupt-cells = <3>; >>> + reg = <0x01f01000 0x1000>, >>> + <0x01f02000 0x2000>; >>> + }; >>> + >>> + soc { >> >> Override by phandle/label instead of duplicating. >> >>> + ranges; >>> + >>> + pinctrl: pinctrl@3001000 { >>> + compatible = "sophgo,sg2000-pinctrl"; >>> + reg = <0x03001000 0x1000>, >>> + <0x05027000 0x1000>; >>> + reg-names = "sys", "rtc"; >>> + }; >>> + }; >>> +}; >>> + >>> + >>> +&clk { >>> + compatible = "sophgo,sg2000-clk"; >> >> >> That's discouraged practice. If you need to define compatible, it means >> the block is not shared between designs and must not be in common DTSI. > > That doesn't come from my series, that's how original cv18xx.dtsi has been You can change the other file to match real hardware. But if original cv18xx.dtsi has incorrect or imprecise compatible, I wonder how does it work.... > designed. Same question as before: do I need to rework it if I will not be able to > test the changes (I don't even posess the relevant HW). But if not, I have > to adapt the same pattern into the new sg2000.dtsi. Best regards, Krzysztof
Hi Krzysztof! On Tue, 2025-02-11 at 09:07 +0100, Krzysztof Kozlowski wrote: > > > > +&clk { > > > > + compatible = "sophgo,sg2000-clk"; > > > > > > > > > That's discouraged practice. If you need to define compatible, it means > > > the block is not shared between designs and must not be in common DTSI. > > > > That doesn't come from my series, that's how original cv18xx.dtsi has been > > You can change the other file to match real hardware. But if original > cv18xx.dtsi has incorrect or imprecise compatible, I wonder how does it > work.... cv18xx.dtsi doesn't have any "compatible". They define it for every SoC individually. So it's same MMIO window, different compatible. Looking into the driver I can tell that even the register map is the same, but they expose (and pre-enable) different subsets on different SoCs.
On 11/02/2025 10:22, Alexander Sverdlin wrote: > Hi Krzysztof! > > On Tue, 2025-02-11 at 09:07 +0100, Krzysztof Kozlowski wrote: >>>>> +&clk { >>>>> + compatible = "sophgo,sg2000-clk"; >>>> >>>> >>>> That's discouraged practice. If you need to define compatible, it means >>>> the block is not shared between designs and must not be in common DTSI. >>> >>> That doesn't come from my series, that's how original cv18xx.dtsi has been >> >> You can change the other file to match real hardware. But if original >> cv18xx.dtsi has incorrect or imprecise compatible, I wonder how does it >> work.... > > cv18xx.dtsi doesn't have any "compatible". They define it for every SoC individually. > So it's same MMIO window, different compatible. Looking into the driver I can tell > that even the register map is the same, but they expose (and pre-enable) different > subsets on different SoCs. OK, so this follows established practice for this soc. Fine with me. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi new file mode 100644 index 000000000000..4e520486cbe5 --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <riscv/sophgo/cv18xx-periph.dtsi> +#include <riscv/sophgo/cv181x.dtsi> + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sophgo,sg2000"; + interrupt-parent = <&gic>; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512MiB */ + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + i-cache-size = <32768>; + d-cache-size = <32768>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-level= <2>; + cache-size = <0x20000>; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + always-on; + clock-frequency = <25000000>; + }; + + gic: interrupt-controller@1f01000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x01f01000 0x1000>, + <0x01f02000 0x2000>; + }; + + soc { + ranges; + + pinctrl: pinctrl@3001000 { + compatible = "sophgo,sg2000-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + }; +}; + + +&clk { + compatible = "sophgo,sg2000-clk"; +};
Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> --- arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi