| Message ID | 20250215-fml13v01_emmc_speed-v1-1-e3bd224ae0e8@hotmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: dts: starfive: fml13v01: increase eMMC bus speed | expand |
| Context | Check | Description |
|---|---|---|
| bjorn/pre-ci_am | fail | Failed to apply series |
Maud Spierings via B4 Relay wrote: > From: Maud Spierings <maud_spierings@hotmail.com> > > The assigned clock speed of 50 MHz is and max-frequency of 100MHz are > limitting this interface which is SDIO 5.0 capable. Sadly at 200MHz it > fails to mount an eMMC drive, 150MHz (really 132 MHz) is the highest it > was able to get. > > This improves the seq read/write performance by 2x~ > > Signed-off-by: Maud Spierings <maud_spierings@hotmail.com> > --- > I put this in this specific dts instead of the common one as I cannot > test if other boards are also able to handle these speeds. Hi Maud, Thanks for the patch! These settings work on my Milk-V Mars board booting off eMMC, but I'm not sure if that means we can just raise the frequency across all the JH7110 boards. The eMMC on my Milk-V mars is a detachable module that identifies as mmcblk0: mmc0:0001 DG4016 14.7 GiB I guess what works might depend on the module too. Is the eMMC on the framework board soldered on? Raising the max-frequency to 200MHz seems right for all boards since we're already saying mmc0 supports HS200 mode. Maybe we could begin by raising the max frequency to 200MHz for all boards, but only assign the 150MHz rate on the framework board? /Emil > > This patch depends on [1] > > [1]: https://lore.kernel.org/all/20250207093618.126636-1-sandie.cao@deepcomputing.io/ > --- > arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts > index 8d9ce8b69a71be78ca57618ae842c9f415648450..1f4bac9f89463a6af844b8f1743bdfa659e612ab 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts > +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts > @@ -11,6 +11,11 @@ / { > compatible = "deepcomputing,fml13v01", "starfive,jh7110"; > }; > > +&mmc0 { > + max-frequency = <200000000>; > + assigned-clock-rates = <150000000>; > +}; > + > &pcie1 { > perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>; > phys = <&pciephy1>; > > --- > base-commit: 0bc08ec1ff5a32449d2b04704173dbf3ebd6b014 > change-id: 20250215-fml13v01_emmc_speed-67812bd9b404 > > Best regards, > -- > Maud Spierings <maud_spierings@hotmail.com> > >
On 2/19/25 3:21 PM, Emil Renner Berthing wrote: > Maud Spierings via B4 Relay wrote: >> From: Maud Spierings <maud_spierings@hotmail.com> >> >> The assigned clock speed of 50 MHz is and max-frequency of 100MHz are >> limitting this interface which is SDIO 5.0 capable. Sadly at 200MHz it >> fails to mount an eMMC drive, 150MHz (really 132 MHz) is the highest it >> was able to get. >> >> This improves the seq read/write performance by 2x~ >> >> Signed-off-by: Maud Spierings <maud_spierings@hotmail.com> >> --- >> I put this in this specific dts instead of the common one as I cannot >> test if other boards are also able to handle these speeds. > Hi Maud, > > Thanks for the patch! > > These settings work on my Milk-V Mars board booting off eMMC, but I'm not sure > if that means we can just raise the frequency across all the JH7110 boards. > The eMMC on my Milk-V mars is a detachable module that identifies as > > mmcblk0: mmc0:0001 DG4016 14.7 GiB > > I guess what works might depend on the module too. Is the eMMC on the framework > board soldered on? No it is also a detachable module, it supports the same interface as most eMMC modules seem to. > Raising the max-frequency to 200MHz seems right for all boards since we're > already saying mmc0 supports HS200 mode. > > Maybe we could begin by raising the max frequency to 200MHz for all boards, > but only assign the 150MHz rate on the framework board? That seems alright with me, I'll send a v2 with max-frequency adjusted in jh7110-common instead. > /Emil kind regards, Maud
diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts index 8d9ce8b69a71be78ca57618ae842c9f415648450..1f4bac9f89463a6af844b8f1743bdfa659e612ab 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts @@ -11,6 +11,11 @@ / { compatible = "deepcomputing,fml13v01", "starfive,jh7110"; }; +&mmc0 { + max-frequency = <200000000>; + assigned-clock-rates = <150000000>; +}; + &pcie1 { perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>; phys = <&pciephy1>;