| Message ID | 20250306175750.22480-6-heylenay@4d2.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add clock controller support for SpacemiT K1 | expand |
| Context | Check | Description |
|---|---|---|
| bjorn/pre-ci_am | success | Success |
| bjorn/build-rv32-defconfig | success | build-rv32-defconfig |
| bjorn/build-rv64-clang-allmodconfig | success | build-rv64-clang-allmodconfig |
| bjorn/build-rv64-gcc-allmodconfig | success | build-rv64-gcc-allmodconfig |
| bjorn/build-rv64-nommu-k210-defconfig | success | build-rv64-nommu-k210-defconfig |
| bjorn/build-rv64-nommu-k210-virt | success | build-rv64-nommu-k210-virt |
| bjorn/checkpatch | success | checkpatch |
| bjorn/dtb-warn-rv64 | success | dtb-warn-rv64 |
| bjorn/header-inline | success | header-inline |
| bjorn/kdoc | success | kdoc |
| bjorn/module-param | success | module-param |
| bjorn/verify-fixes | success | verify-fixes |
| bjorn/verify-signedoff | success | verify-signedoff |
On Thu, Mar 06, 2025 at 05:57:50PM +0000, Haylen Chu wrote: > The control register for TWSI8 clocks, APBC_TWSI8_CLK_RST, contains mux > selection bits, reset assertion bit and enable bits for function and bus > clocks. It has a quirk that reading always results in zero. > > As a workaround, let's hardcode the mux value as zero to select > pll1_d78_31p5 as parent and treat twsi8_clk as a gate, whose enable mask > is combined from the real bus and function clocks to avoid the > write-only register being shared between two clk_hws, in which case > updates of one clk_hw zero the other's bits. > > With a 1:1 factor serving as placeholder for the bus clock, the I2C-8 > controller could be brought up, which is essential for boards attaching > power-management chips to it. > > Signed-off-by: Haylen Chu <heylenay@4d2.org> > --- > drivers/clk/spacemit/ccu-k1.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c > index 5974a0a1b5f6..44db48ae7131 100644 > --- a/drivers/clk/spacemit/ccu-k1.c > +++ b/drivers/clk/spacemit/ccu-k1.c > @@ -558,6 +558,10 @@ static CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, > APBC_TWSI7_CLK_RST, > 4, 3, BIT(1), > 0); > +static CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), > + APBC_TWSI8_CLK_RST, > + BIT(1) | BIT(0), > + 0); > > static const struct clk_parent_data timer_parents[] = { > CCU_PARENT_HW(pll1_d192_12p8), > @@ -795,6 +799,8 @@ static CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), > APBC_TWSI7_CLK_RST, > BIT(0), > 0); > +static CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), > + 1, 1); > > static CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), > APBC_TIMERS1_CLK_RST, > -- > 2.48.1 > Oops, I don't split out the twsi8-related definitions completely from PATCH 3, causing building errors with only PATCH 3 applied. Will fix it in the next version. Best regards, Haylen Chu
diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 5974a0a1b5f6..44db48ae7131 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -558,6 +558,10 @@ static CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, APBC_TWSI7_CLK_RST, 4, 3, BIT(1), 0); +static CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), + APBC_TWSI8_CLK_RST, + BIT(1) | BIT(0), + 0); static const struct clk_parent_data timer_parents[] = { CCU_PARENT_HW(pll1_d192_12p8), @@ -795,6 +799,8 @@ static CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI7_CLK_RST, BIT(0), 0); +static CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), + 1, 1); static CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST,
The control register for TWSI8 clocks, APBC_TWSI8_CLK_RST, contains mux selection bits, reset assertion bit and enable bits for function and bus clocks. It has a quirk that reading always results in zero. As a workaround, let's hardcode the mux value as zero to select pll1_d78_31p5 as parent and treat twsi8_clk as a gate, whose enable mask is combined from the real bus and function clocks to avoid the write-only register being shared between two clk_hws, in which case updates of one clk_hw zero the other's bits. With a 1:1 factor serving as placeholder for the bus clock, the I2C-8 controller could be brought up, which is essential for boards attaching power-management chips to it. Signed-off-by: Haylen Chu <heylenay@4d2.org> --- drivers/clk/spacemit/ccu-k1.c | 6 ++++++ 1 file changed, 6 insertions(+)