[GIT,PULL] RISC-V Devicetrees for v6.15

Message ID	20250318-favorite-presuming-bf2fcf55bf6a@spud (mailing list archive)
State	Handled Elsewhere
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> Date: Tue, 18 Mar 2025 11:57:31 +0000 From: Conor Dooley <conor@kernel.org> To: soc@kernel.org Cc: conor@kernel.org, linux-riscv@lists.infradead.org Subject: [GIT PULL] RISC-V Devicetrees for v6.15 Message-ID: <20250318-favorite-presuming-bf2fcf55bf6a@spud> MIME-Version: 1.0 Precedence: list Content-Type: multipart/mixed; boundary="===============6220209905542224621==" Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	[GIT,PULL] RISC-V Devicetrees for v6.15 \| expand [GIT,PULL] RISC-V Devicetrees for v6.15

Message ID

20250318-favorite-presuming-bf2fcf55bf6a@spud (mailing list archive)

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Handled Elsewhere

Headers

Date: Tue, 18 Mar 2025 11:57:31 +0000
From: Conor Dooley <conor@kernel.org>
To: soc@kernel.org
Cc: conor@kernel.org, linux-riscv@lists.infradead.org
Subject: [GIT PULL] RISC-V Devicetrees for v6.15
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Series

[GIT,PULL] RISC-V Devicetrees for v6.15 | expand

Message

Conor Dooley March 18, 2025, 11:57 a.m. UTC

Hey Arnd,

Not too much this window, was hoping to get the k230 (canaan soc) this
time around, but the clock side of things was not ready.

Cheers,
Conor.

The following changes since commit 2014c95afecee3e76ca4a56956a936e23283f05b:

  Linux 6.14-rc1 (2025-02-02 15:39:26 -0800)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ riscv-dt-for-v6.15

for you to fetch changes up to 38818f7c9c179351334b1faffc4d40bd28cc9c72:

  riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port (2025-02-18 16:32:25 +0000)

----------------------------------------------------------------
RISC-V Devicetrees for v6.15

Starfive:
All changes for jh7110-based boards including the removal of a dac
that does not exist and the addition of usb3 support on the star64 board
and pcie on the framework mainboard.

Microchip:
Update pcie reg properties to fix a mistake originally describing them.
Here rather than in fixes, since the driver maintains support for the
old format.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

----------------------------------------------------------------
Conor Dooley (2):
      riscv: dts: microchip: update pcie reg properties to new format
      riscv: dts: starfive: remove non-existent dac from jh7110

E Shattow (2):
      riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers
      riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port

Sandie Cao (1):
      riscv: dts: starfive: fml13v01: enable pcie1

Shengyu Qu (1):
      riscv: dts: starfive: Unify regulator naming scheme

 .../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi |  5 ++--
 .../boot/dts/microchip/mpfs-m100pfs-fabric.dtsi    |  5 ++--
 .../boot/dts/microchip/mpfs-polarberry-fabric.dtsi |  5 ++--
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi    |  8 +----
 .../dts/starfive/jh7110-deepcomputing-fml13v01.dts | 34 ++++++++++++++++++++++
 .../boot/dts/starfive/jh7110-pine64-star64.dts     |  5 ++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi           |  2 ++
 7 files changed, 51 insertions(+), 13 deletions(-)

[GIT,PULL] RISC-V Devicetrees for v6.15

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