@@ -28,6 +28,25 @@ led1 {
default-state = "on";
};
};
+
+ usb3_vhub: regulator-vhub-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "USB30_VHUB";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb3_vbus: regulator-vbus-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "USB30_VBUS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&uart0 {
@@ -35,3 +54,39 @@ &uart0 {
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+ vbus-supply = <&usb3_vbus>;
+
+ usb@0 {
+ dr_mode = "host";
+ phy_type = "utmi";
+ snps,hsphy_interface = "utmi";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1u2-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis_rxdet_inp3_quirk;
+ snps,xhci-trb-ent-quirk;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hub@1 {
+ compatible = "usb2109,817";
+ reg = <0x1>;
+ vdd-supply = <&usb3_vhub>;
+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+ };
+ };
+};
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/clock/spacemit,k1-ccu.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/dts-v1/;
/ {
@@ -350,6 +352,14 @@ soc {
dma-noncoherent;
ranges;
+ dram_range0: dram_range@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
+ #interconnect-cells = <0>;
+ status = "okay";
+ };
+
syscon_rcpu: system-controller@c0880000 {
compatible = "spacemit,k1-syscon-rcpu";
reg = <0x0 0xc0880000 0x0 0x2048>;
@@ -362,6 +372,48 @@ syscon_rcpu2: system-controller@c0888000 {
#reset-cells = <1>;
};
+ usb3: usb@c0a00000 {
+ compatible = "spacemit,k1-dwc3";
+ clocks = <&syscon_apmu CLK_USB30>;
+ clock-names = "usbdrd30";
+ interrupt-parent = <&plic>;
+ interrupts = <149>;
+ interconnects = <&dram_range0>;
+ interconnect-names = "dma-mem";
+ ranges = <0x0 0x0 0x0 0xc0a00000 0x0 0x10000>;
+ resets = <&syscon_apmu RESET_USB3_0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x0 0x0 0x10000>;
+ interrupt-parent = <&plic>;
+ interrupts = <125>;
+ phys = <&usb3_phy0>, <&usb3_phy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
+
+ usb3_phy0: usb-phy@0xc0a30000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0x0 0xc0a30000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_USB30>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb3_phy1: combphy@c0b10000 {
+ compatible = "spacemit,k1-combphy";
+ reg = <0x0 0xc0b10000 0x0 0x800>,
+ <0x0 0xd4282910 0x0 0x400>;
+ reg-names = "phy_ctrl", "phy_sel";
+ resets = <&syscon_apmu RESET_PCIE0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
syscon_apbc: system-control@d4015000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
Add USB 3.0 support for the SpacemiT K1 SoC, including the following components: - USB 2.0 PHY node (usb_phy2) - USB 3.0 combo PHY node (usb_phy3) - USB 3.0 host controller (dwc3 glue + core) - USB 3.0 hub and vbus regulator (usb3_vhub, usb3_vbus) - DRAM interconnect node for USB DMA ("dma-mem") The `usb3_vbus` and `usb3_vhub` regulator node provides a fixed 5V supply to power the onboard USB 3.0 hub and usb vbus. On K1, some DMA transfers from devices to memory use separate buses with different DMA address translation rules from the parent node. We express this relationship through the interconnects node("dma-mem"). Signed-off-by: Ze Huang <huangze@whut.edu.cn> --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 55 +++++++++++++++++++++++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 52 +++++++++++++++++++++++ 2 files changed, 107 insertions(+)