| Message ID | IA1PR20MB495310F06009AA884D0612A1BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: dts: allwinner: d1: Add PMU event node | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 9f944d2e0ab3 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 4 and now 4 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 9 this patch: 9 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | fail | Errors and warnings before: 12 this patch: 36 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 45 lines checked |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
On Sat, Aug 26, 2023 at 04:38:53PM +0800, Inochi Amaoto wrote: > D1 has several pmu events supported by opensbi. > These events can be used by perf for profiling. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Could you please include a link to some documentation as to where these values came from? I know several people have had some trouble with understanding the pmu DT stuff & having some documentation would make this an in-tree end-to-end example. Thanks, Conor. > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 40 +++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 8275630af977..d9031ccdec89 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -72,5 +72,45 @@ plic: interrupt-controller@10000000 { > #address-cells = <0>; > #interrupt-cells = <2>; > }; > + > + pmu { > + compatible = "riscv,pmu"; > + riscv,event-to-mhpmcounters = > + <0x00003 0x00003 0x00000008>, > + <0x00004 0x00004 0x00000010>, > + <0x00005 0x00005 0x00000200>, > + <0x00006 0x00006 0x00000100>, > + <0x10000 0x10000 0x00004000>, > + <0x10001 0x10001 0x00008000>, > + <0x10002 0x10002 0x00010000>, > + <0x10003 0x10003 0x00020000>, > + <0x10019 0x10019 0x00000040>, > + <0x10021 0x10021 0x00000020>; > + riscv,event-to-mhpmevent = > + <0x00003 0x00000000 0x00000001>, > + <0x00004 0x00000000 0x00000002>, > + <0x00005 0x00000000 0x00000007>, > + <0x00006 0x00000000 0x00000006>, > + <0x0000a 0x00000000 0x0000000b>, > + <0x10000 0x00000000 0x0000000c>, > + <0x10001 0x00000000 0x0000000d>, > + <0x10002 0x00000000 0x0000000e>, > + <0x10003 0x00000000 0x0000000f>, > + <0x10019 0x00000000 0x00000004>, > + <0x10021 0x00000000 0x00000003>; > + riscv,raw-event-to-mhpmcounters = > + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, > + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, > + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, > + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, > + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, > + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, > + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, > + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, > + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, > + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, > + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, > + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; > + }; > }; > }; > -- > 2.41.0 >
The DT field of riscv,pmu for opensbi can be found on: https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md The value can be found in the R1S0 version of C906 documentation: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf The meaning of T-HEAD events can be found in this patch: https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com The patch above also provides documentation for T-HEAD events and a example that shows how to use perf with T-HEAD events. >On Sat, Aug 26, 2023 at 04:38:53PM +0800, Inochi Amaoto wrote: >> D1 has several pmu events supported by opensbi. >> These events can be used by perf for profiling. >> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > >Could you please include a link to some documentation as to where these >values came from? I know several people have had some trouble with >understanding the pmu DT stuff & having some documentation would make >this an in-tree end-to-end example. > >Thanks, >Conor. >
On Sat, Aug 26, 2023 at 07:25:43PM +0800, Inochi Amaoto wrote: > >On Sat, Aug 26, 2023 at 04:38:53PM +0800, Inochi Amaoto wrote: > >> D1 has several pmu events supported by opensbi. > >> These events can be used by perf for profiling. > >> > >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > > > >Could you please include a link to some documentation as to where these > >values came from? I know several people have had some trouble with > >understanding the pmu DT stuff & having some documentation would make > >this an in-tree end-to-end example. > The DT field of riscv,pmu for opensbi can be found on: > https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md There's an actual dt-binding for this. > The value can be found in the R1S0 version of C906 documentation: > https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf > > The meaning of T-HEAD events can be found in this patch: > https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com > > The patch above also provides documentation for T-HEAD events and a example > that shows how to use perf with T-HEAD events. What I meant was can you provide links to this in the commit messages so that people have a way to find the documentation.
>>> On Sat, Aug 26, 2023 at 04:38:53PM +0800, Inochi Amaoto wrote: >>>> D1 has several pmu events supported by opensbi. >>>> These events can be used by perf for profiling. >>>> >>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> >>> >>> Could you please include a link to some documentation as to where these >>> values came from? I know several people have had some trouble with >>> understanding the pmu DT stuff & having some documentation would make >>> this an in-tree end-to-end example. > >> The DT field of riscv,pmu for opensbi can be found on: >> https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md > >There's an actual dt-binding for this. > >> The value can be found in the R1S0 version of C906 documentation: >> https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf >> >> The meaning of T-HEAD events can be found in this patch: >> https://lore.kernel.org/linux-perf-users/IA1PR20MB4953DD82D0116EC291C21777BBE2A@IA1PR20MB4953.namprd20.prod.outlook.com >> >> The patch above also provides documentation for T-HEAD events and a example >> that shows how to use perf with T-HEAD events. > >What I meant was can you provide links to this in the commit messages so >that people have a way to find the documentation. OK, I will setup a new patch to cover these info.
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 8275630af977..d9031ccdec89 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -72,5 +72,45 @@ plic: interrupt-controller@10000000 { #address-cells = <0>; #interrupt-cells = <2>; }; + + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmcounters = + <0x00003 0x00003 0x00000008>, + <0x00004 0x00004 0x00000010>, + <0x00005 0x00005 0x00000200>, + <0x00006 0x00006 0x00000100>, + <0x10000 0x10000 0x00004000>, + <0x10001 0x10001 0x00008000>, + <0x10002 0x10002 0x00010000>, + <0x10003 0x10003 0x00020000>, + <0x10019 0x10019 0x00000040>, + <0x10021 0x10021 0x00000020>; + riscv,event-to-mhpmevent = + <0x00003 0x00000000 0x00000001>, + <0x00004 0x00000000 0x00000002>, + <0x00005 0x00000000 0x00000007>, + <0x00006 0x00000000 0x00000006>, + <0x0000a 0x00000000 0x0000000b>, + <0x10000 0x00000000 0x0000000c>, + <0x10001 0x00000000 0x0000000d>, + <0x10002 0x00000000 0x0000000e>, + <0x10003 0x00000000 0x0000000f>, + <0x10019 0x00000000 0x00000004>, + <0x10021 0x00000000 0x00000003>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>, + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>, + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>, + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>, + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>, + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>, + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>, + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>, + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>, + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>, + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; + }; }; };
D1 has several pmu events supported by opensbi. These events can be used by perf for profiling. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+)