diff mbox series

riscv: dts: sophgo: Add i2c device support for sg2042

Message ID IA1PR20MB49531864C828FE90C4C25D1BBBB42@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive)
State Superseded
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Series riscv: dts: sophgo: Add i2c device support for sg2042 | expand

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Context Check Description
conchuod/vmtest-for-next-PR success PR summary
conchuod/patch-1-test-1 success .github/scripts/patches/tests/build_rv32_defconfig.sh
conchuod/patch-1-test-2 success .github/scripts/patches/tests/build_rv64_clang_allmodconfig.sh
conchuod/patch-1-test-3 success .github/scripts/patches/tests/build_rv64_gcc_allmodconfig.sh
conchuod/patch-1-test-4 success .github/scripts/patches/tests/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-1-test-5 success .github/scripts/patches/tests/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-1-test-6 success .github/scripts/patches/tests/checkpatch.sh
conchuod/patch-1-test-7 success .github/scripts/patches/tests/dtb_warn_rv64.sh
conchuod/patch-1-test-8 success .github/scripts/patches/tests/header_inline.sh
conchuod/patch-1-test-9 success .github/scripts/patches/tests/kdoc.sh
conchuod/patch-1-test-10 success .github/scripts/patches/tests/module_param.sh
conchuod/patch-1-test-11 success .github/scripts/patches/tests/verify_fixes.sh
conchuod/patch-1-test-12 success .github/scripts/patches/tests/verify_signedoff.sh

Commit Message

Inochi Amaoto July 26, 2024, 1:07 a.m. UTC 
The i2c ip of sg2042 is a standard Synopsys i2c ip, which is already
supported by the mainline kernel.

Add i2c device node for sg2042.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 54 +++++++++++++++++++++++++-
 1 file changed, 53 insertions(+), 1 deletion(-)

--
2.45.2

Comments

Chen Wang July 29, 2024, 1:45 a.m. UTC | #1 
On 2024/7/26 9:07, Inochi Amaoto wrote:
> The i2c ip of sg2042 is a standard Synopsys i2c ip, which is already
> supported by the mainline kernel.
>
> Add i2c device node for sg2042.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
>   arch/riscv/boot/dts/sophgo/sg2042.dtsi | 54 +++++++++++++++++++++++++-
>   1 file changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index 34c802bd3f9b..eebd6817520e 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -44,8 +44,61 @@ soc: soc {
>   		compatible = "simple-bus";
>   		#address-cells = <2>;
>   		#size-cells = <2>;
> +		interrupt-parent = <&intc>;

I would suggest this change (use common interrupt-parent for soc) in 
another separated patch and this would looks more clear.

Then this patch is only for i2c related changes.

>   		ranges;
>
> +		i2c0: i2c@7030005000 {
> +			compatible = "snps,designware-i2c";
> +			reg = <0x70 0x30005000 0x0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&clkgen GATE_CLK_APB_I2C>;
> +			clock-names = "ref";
> +			clock-frequency = <100000>;
> +			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
> +			resets = <&rstgen RST_I2C0>;
> +			status = "disabled";
> +		};
> +
> +		i2c1: i2c@7030006000 {
> +			compatible = "snps,designware-i2c";
> +			reg = <0x70 0x30006000 0x0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&clkgen GATE_CLK_APB_I2C>;
> +			clock-names = "ref";
> +			clock-frequency = <100000>;
> +			interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
> +			resets = <&rstgen RST_I2C1>;
> +			status = "disabled";
> +		};
> +
> +		i2c2: i2c@7030007000 {
> +			compatible = "snps,designware-i2c";
> +			reg = <0x70 0x30007000 0x0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&clkgen GATE_CLK_APB_I2C>;
> +			clock-names = "ref";
> +			clock-frequency = <100000>;
> +			interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
> +			resets = <&rstgen RST_I2C2>;
> +			status = "disabled";
> +		};
> +
> +		i2c3: i2c@7030008000 {
> +			compatible = "snps,designware-i2c";
> +			reg = <0x70 0x30008000 0x0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&clkgen GATE_CLK_APB_I2C>;
> +			clock-names = "ref";
> +			clock-frequency = <100000>;
> +			interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
> +			resets = <&rstgen RST_I2C3>;
> +			status = "disabled";
> +		};
> +
>   		pllclk: clock-controller@70300100c0 {
>   			compatible = "sophgo,sg2042-pll";
>   			reg = <0x70 0x300100c0 0x0 0x40>;
> @@ -388,7 +441,6 @@ rstgen: reset-controller@7030013000 {
>   		uart0: serial@7040000000 {
>   			compatible = "snps,dw-apb-uart";
>   			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
> -			interrupt-parent = <&intc>;
I would prefer this change in a separated patch which has been mentioned 
upon.
>   			interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>   			clock-frequency = <500000000>;
>   			clocks = <&clkgen GATE_CLK_UART_500M>,
> --
> 2.45.2
>
Inochi Amaoto July 29, 2024, 2:02 a.m. UTC | #2 
On Mon, Jul 29, 2024 at 09:45:42AM GMT, Chen Wang wrote:
> 
> On 2024/7/26 9:07, Inochi Amaoto wrote:
> > The i2c ip of sg2042 is a standard Synopsys i2c ip, which is already
> > supported by the mainline kernel.
> > 
> > Add i2c device node for sg2042.
> > 
> > Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> > ---
> >   arch/riscv/boot/dts/sophgo/sg2042.dtsi | 54 +++++++++++++++++++++++++-
> >   1 file changed, 53 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > index 34c802bd3f9b..eebd6817520e 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> > @@ -44,8 +44,61 @@ soc: soc {
> >   		compatible = "simple-bus";
> >   		#address-cells = <2>;
> >   		#size-cells = <2>;
> > +		interrupt-parent = <&intc>;
> 
> I would suggest this change (use common interrupt-parent for soc) in another
> separated patch and this would looks more clear.
> 
> Then this patch is only for i2c related changes.
> 

Yeah, that is kind of reasonable. I will separate it.

> >   		ranges;
> > 
> > +		i2c0: i2c@7030005000 {
> > +			compatible = "snps,designware-i2c";
> > +			reg = <0x70 0x30005000 0x0 0x1000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			clocks = <&clkgen GATE_CLK_APB_I2C>;
> > +			clock-names = "ref";
> > +			clock-frequency = <100000>;
> > +			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
> > +			resets = <&rstgen RST_I2C0>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c1: i2c@7030006000 {
> > +			compatible = "snps,designware-i2c";
> > +			reg = <0x70 0x30006000 0x0 0x1000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			clocks = <&clkgen GATE_CLK_APB_I2C>;
> > +			clock-names = "ref";
> > +			clock-frequency = <100000>;
> > +			interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
> > +			resets = <&rstgen RST_I2C1>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c2: i2c@7030007000 {
> > +			compatible = "snps,designware-i2c";
> > +			reg = <0x70 0x30007000 0x0 0x1000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			clocks = <&clkgen GATE_CLK_APB_I2C>;
> > +			clock-names = "ref";
> > +			clock-frequency = <100000>;
> > +			interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
> > +			resets = <&rstgen RST_I2C2>;
> > +			status = "disabled";
> > +		};
> > +
> > +		i2c3: i2c@7030008000 {
> > +			compatible = "snps,designware-i2c";
> > +			reg = <0x70 0x30008000 0x0 0x1000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			clocks = <&clkgen GATE_CLK_APB_I2C>;
> > +			clock-names = "ref";
> > +			clock-frequency = <100000>;
> > +			interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
> > +			resets = <&rstgen RST_I2C3>;
> > +			status = "disabled";
> > +		};
> > +
> >   		pllclk: clock-controller@70300100c0 {
> >   			compatible = "sophgo,sg2042-pll";
> >   			reg = <0x70 0x300100c0 0x0 0x40>;
> > @@ -388,7 +441,6 @@ rstgen: reset-controller@7030013000 {
> >   		uart0: serial@7040000000 {
> >   			compatible = "snps,dw-apb-uart";
> >   			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
> > -			interrupt-parent = <&intc>;
> I would prefer this change in a separated patch which has been mentioned
> upon.
> >   			interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
> >   			clock-frequency = <500000000>;
> >   			clocks = <&clkgen GATE_CLK_UART_500M>,
> > --
> > 2.45.2
> >
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 34c802bd3f9b..eebd6817520e 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -44,8 +44,61 @@  soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;
+		interrupt-parent = <&intc>;
 		ranges;

+		i2c0: i2c@7030005000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x70 0x30005000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clkgen GATE_CLK_APB_I2C>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rstgen RST_I2C0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@7030006000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x70 0x30006000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clkgen GATE_CLK_APB_I2C>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rstgen RST_I2C1>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@7030007000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x70 0x30007000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clkgen GATE_CLK_APB_I2C>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rstgen RST_I2C2>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@7030008000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x70 0x30008000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clkgen GATE_CLK_APB_I2C>;
+			clock-names = "ref";
+			clock-frequency = <100000>;
+			interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&rstgen RST_I2C3>;
+			status = "disabled";
+		};
+
 		pllclk: clock-controller@70300100c0 {
 			compatible = "sophgo,sg2042-pll";
 			reg = <0x70 0x300100c0 0x0 0x40>;
@@ -388,7 +441,6 @@  rstgen: reset-controller@7030013000 {
 		uart0: serial@7040000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
-			interrupt-parent = <&intc>;
 			interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
 			clock-frequency = <500000000>;
 			clocks = <&clkgen GATE_CLK_UART_500M>,