| Message ID | IA1PR20MB49538E6F9B462DD40E98C998BBB3A@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Change the sg2042 timer layout to fit aclint format | expand |
On Mon, Nov 13, 2023 at 10:23:59AM +0800, Inochi Amaoto wrote: > To make thead aclint timer more closer to the aclint spec, use two regs > to represent the mtime and mtimecmp. In the devicetree patch you say: "Change the timer layout in the dtb to fit the format that needed by the SBI." That seems like a far more important thing to say in the binding patch, since that is where the ABI is set. You also provide two links to discussion on the mailing list for opensbi, but provide no context in the commit message here for why they're relevant. The 005738 one doesn't seem to be relevant at all? Could you please resubmit this with a better commit message that explains why the ABI here needs to change? Thanks, Conor. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer") > Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html > Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005738.html > Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc > --- > .../devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml > index fbd235650e52..c3080962d902 100644 > --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml > +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml > @@ -17,7 +17,7 @@ properties: > - const: thead,c900-aclint-mtimer > > reg: > - maxItems: 1 > + maxItems: 2 > > interrupts-extended: > minItems: 1 > @@ -38,6 +38,7 @@ examples: > <&cpu2intc 7>, > <&cpu3intc 7>, > <&cpu4intc 7>; > - reg = <0xac000000 0x00010000>; > + reg = <0xac000000 0x00000000>, > + <0xac000000 0x0000c000>; > }; > ... > -- > 2.42.1 >
diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml index fbd235650e52..c3080962d902 100644 --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml @@ -17,7 +17,7 @@ properties: - const: thead,c900-aclint-mtimer reg: - maxItems: 1 + maxItems: 2 interrupts-extended: minItems: 1 @@ -38,6 +38,7 @@ examples: <&cpu2intc 7>, <&cpu3intc 7>, <&cpu4intc 7>; - reg = <0xac000000 0x00010000>; + reg = <0xac000000 0x00000000>, + <0xac000000 0x0000c000>; }; ...
To make thead aclint timer more closer to the aclint spec, use two regs to represent the mtime and mtimecmp. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer") Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005738.html Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc --- .../devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.42.1