mbox series

[GIT,PULL] RISC-V updates for v5.5-rc5

Message ID alpine.DEB.2.21.9999.2001042202460.484919@viisi.sifive.com (mailing list archive)
State Accepted, archived
Headers show
Series [GIT,PULL] RISC-V updates for v5.5-rc5 | expand

Pull-request

git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.5-rc5

Message

Paul Walmsley Jan. 5, 2020, 6:04 a.m. UTC
Linus,

The following changes since commit fd6988496e79a6a4bdb514a4655d2920209eb85d:

  Linux 5.5-rc4 (2019-12-29 15:29:16 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.5-rc5

for you to fetch changes up to 0e194d9da198936fe4fb4c1e031de0f7791c09b8:

  Documentation: riscv: add patch acceptance guidelines (2020-01-04 21:49:01 -0800)

----------------------------------------------------------------
RISC-V updates for v5.5-rc5

Several fixes for RISC-V:

- Fix function graph trace support

- Prefix the CSR IRQ_* macro names with "RV_", to avoid collisions
  with macros elsewhere in the Linux kernel tree named "IRQ_TIMER"

- Use __pa_symbol() when computing the physical address of a kernel
  symbol, rather than __pa()

- Mark the RISC-V port as supporting GCOV

One DT addition:

- Describe the L2 cache controller in the FU540 DT file

One documentation update:

- Add patch acceptance guideline documentation

----------------------------------------------------------------
Paul Walmsley (2):
      riscv: prefix IRQ_ macro names with an RV_ namespace
      Documentation: riscv: add patch acceptance guidelines

Yash Shah (1):
      riscv: dts: Add DT support for SiFive L2 cache controller

Zong Li (4):
      riscv: mm: use __pa_symbol for kernel symbols
      riscv: gcov: enable gcov for RISC-V
      riscv: ftrace: correct the condition logic in function graph tracer
      clocksource: riscv: add notrace to riscv_sched_clock

 .../debug/gcov-profile-all/arch-support.txt        |  2 +-
 Documentation/process/index.rst                    |  1 +
 Documentation/riscv/index.rst                      |  1 +
 Documentation/riscv/patch-acceptance.rst           | 35 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 arch/riscv/Kconfig                                 |  1 +
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi         | 15 ++++++++++
 arch/riscv/include/asm/csr.h                       | 18 +++++------
 arch/riscv/kernel/ftrace.c                         |  2 +-
 arch/riscv/kernel/irq.c                            |  6 ++--
 arch/riscv/mm/init.c                               | 12 ++++----
 drivers/clocksource/timer-riscv.c                  |  2 +-
 drivers/irqchip/irq-sifive-plic.c                  |  2 +-
 13 files changed, 76 insertions(+), 22 deletions(-)
 create mode 100644 Documentation/riscv/patch-acceptance.rst

Kernel object size difference:
   text	   data	    bss	    dec	    hex	filename
6896189	2329828	 313920	9539937	 919161	vmlinux.rv64.orig
6896191	2329892	 313920	9540003	 9191a3	vmlinux.rv64.patched
6656496	1939040	 257576	8853112	 871678	vmlinux.rv32.orig
6656498	1939040	 257576	8853114	 87167a	vmlinux.rv32.patched
1171674	 353368	 130024	1655066	 19411a	vmlinux.nommu_virt.orig
1171674	 353368	 130024	1655066	 19411a	vmlinux.nommu_virt.patched

Comments

pr-tracker-bot@kernel.org Jan. 5, 2020, 7:35 p.m. UTC | #1
The pull request you sent on Sat, 4 Jan 2020 22:04:16 -0800 (PST):

> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.5-rc5

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/768fc661d12559b0dbd99d941b3bf28fe92fd365

Thank you!