| Message ID | ebcfe039b13097e53b3721f56a45d99807f2925b.1722457123.git.jan.kiszka@siemens.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: jh7110: Fix configuration for on-chip USB 2.0 support | expand |
On Wed, 31 Jul 2024 22:18:41 +0200, Jan Kiszka wrote: > From: Jan Kiszka <jan.kiszka@siemens.com> > > Analogously to the PCI PHY, access to sys_syscon is needed to connect > the USB PHY to its controller. > > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> > --- > CC: Rob Herring <robh@kernel.org> > CC: Krzysztof Kozlowski <krzk+dt@kernel.org> > CC: Conor Dooley <conor+dt@kernel.org> > --- > .../bindings/phy/starfive,jh7110-usb-phy.yaml | 11 +++++++++++ > 1 file changed, 11 insertions(+) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml index 269e9f9f12b6..eaf0050c6f17 100644 --- a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml @@ -19,6 +19,16 @@ properties: "#phy-cells": const: 0 + starfive,sys-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller sys_syscon node. + - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY. + description: + The phandle to System Register Controller syscon node and the PHY connect offset + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB controller. + clocks: items: - description: PHY 125m @@ -47,4 +57,5 @@ examples: <&stgcrg 6>; clock-names = "125m", "app_125m"; #phy-cells = <0>; + starfive,sys-syscon = <&sys_syscon 0x18>; };