| Message ID | mhng-109b0503-bc7c-4da8-8621-28aec8d9df59@palmer-ri-x1c9 (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [GIT,PULL] RISC-V Patches for the 5.16 Merge Window, Part 1 | expand |
On Fri, 12 Nov 2021 09:32:15 PST (-0800), Palmer Dabbelt wrote: > The following changes since commit 3f2401f47d29d669e2cb137709d10dd4c156a02f: > > RISC-V: Add hypervisor extension related CSR defines (2021-10-04 04:54:55 -0400) > > are available in the Git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.16-mw1 > > for you to fetch changes up to ffa7a9141bb70702744a312f904b190ca064bdd7: > > riscv: defconfig: enable DRM_NOUVEAU (2021-10-27 14:36:09 -0700) > > ---------------------------------------------------------------- > RISC-V Patches for the 5.16 Merge Window, Part 1 > > * Support for time namespaces in the VDSO, along with some associated > cleanups. > * Support for building rv32 randconfigs. > * Improvements to the XIP port that allow larger kernels to function > * Various device tree cleanups for both the SiFive and Microchip boards > * A handful of defconfig updates, including enabling Nouveau. > > There are also various small cleanups. I forgot to send along my conflict resolutions: diff --cc arch/riscv/Kconfig index dcd7afcd98ef,a34c531be4e7..821252b65f89 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@@ -62,8 -62,6 +62,7 @@@ config RISC select GENERIC_SCHED_CLOCK select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL if MMU && 64BIT + select GENERIC_VDSO_TIME_NS if HAVE_GENERIC_VDSO - select HANDLE_DOMAIN_IRQ select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL diff --cc arch/riscv/Makefile index 9247407b95d6,7f19b784e649..5927c94302b8 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@@ -137,16 -136,3 +136,13 @@@ zinstall: install-image = Image.g install zinstall: $(CONFIG_SHELL) $(srctree)/$(boot)/install.sh $(KERNELRELEASE) \ $(boot)/$(install-image) System.map "$(INSTALL_PATH)" + - archclean: - $(Q)$(MAKE) $(clean)=$(boot) - +PHONY += rv32_randconfig +rv32_randconfig: + $(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/riscv/configs/32-bit.config \ + -f $(srctree)/Makefile randconfig + +PHONY += rv64_randconfig +rv64_randconfig: + $(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/riscv/configs/64-bit.config \ + -f $(srctree)/Makefile randconfig Sorry if anything else went off the rails, being on the new computer has be a bit off kilter. I think I got all my PGP stuff sorted out yesterday. > > ---------------------------------------------------------------- > Dimitri John Ledkov (1): > riscv: set default pm_power_off to NULL > > Heinrich Schuchardt (1): > riscv: defconfig: enable DRM_NOUVEAU > > Kefeng Wang (1): > riscv/vdso: Drop unneeded part due to merge issue > > Krzysztof Kozlowski (11): > dt-bindings: mmc: cdns: document Microchip MPFS MMC/SDHCI controller > riscv: dts: microchip: drop duplicated nodes > riscv: dts: microchip: fix board compatible > riscv: dts: microchip: drop duplicated MMC/SDHC node > riscv: dts: microchip: drop unused pinctrl-names > riscv: dts: microchip: use vendor compatible for Cadence SD4HC > riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible > riscv: dts: sifive: fix Unleashed board compatible > riscv: dts: sifive: drop duplicated nodes and properties in sifive > riscv: dts: microchip: add missing compatibles for clint and plic > riscv: dts: sifive: add missing compatible for plic > > Palmer Dabbelt (3): > Merge remote-tracking branch 'palmer/riscv-vdso-cleanup' into for-next > Merge tag 'for-riscv' of https://git.kernel.org/pub/scm/virt/kvm/kvm.git into for-next > Merge tag 'riscv-sifive-dt-5.16' of git://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into for-next > > Randy Dunlap (1): > riscv: add rv32 and rv64 randconfig build targets > > Tong Tiangen (1): > riscv/vdso: Add support for time namespaces > > Vineet Gupta (1): > riscv: mm: don't advertise 1 num_asid for 0 asid bits > > Vitaly Wool (1): > riscv: remove .text section size limitation for XIP > > .../devicetree/bindings/mmc/cdns,sdhci.yaml | 1 + > arch/riscv/Kconfig | 1 + > arch/riscv/Makefile | 10 + > .../dts/microchip/microchip-mpfs-icicle-kit.dts | 18 +- > arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 40 +--- > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +- > .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 10 +- > .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 7 +- > arch/riscv/configs/32-bit.config | 2 + > arch/riscv/configs/64-bit.config | 2 + > arch/riscv/configs/defconfig | 7 +- > arch/riscv/include/asm/page.h | 2 + > arch/riscv/include/asm/pgtable.h | 6 +- > arch/riscv/include/asm/syscall.h | 1 + > arch/riscv/include/asm/vdso.h | 13 +- > arch/riscv/include/asm/vdso/gettimeofday.h | 7 + > arch/riscv/kernel/head.S | 12 + > arch/riscv/kernel/reset.c | 12 +- > arch/riscv/kernel/syscall_table.c | 1 - > arch/riscv/kernel/vdso.c | 261 +++++++++++++++++---- > arch/riscv/kernel/vdso/vdso.lds.S | 6 +- > arch/riscv/kernel/vmlinux-xip.lds.S | 10 +- > arch/riscv/mm/context.c | 8 +- > arch/riscv/mm/init.c | 7 +- > 24 files changed, 311 insertions(+), 135 deletions(-) > create mode 100644 arch/riscv/configs/32-bit.config > create mode 100644 arch/riscv/configs/64-bit.config
On Fri, Nov 12, 2021 at 9:32 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > RISC-V Patches for the 5.16 Merge Window, Part 1 What's "part 1" about this? This was sent on a Friday of the second week of the merge window. No way in hell is there going to be a "part 2" that I would possibly accept at this stage. It's late as-is. Linus
On Fri, 12 Nov 2021 13:37:46 PST (-0800), Linus Torvalds wrote: > On Fri, Nov 12, 2021 at 9:32 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: >> >> RISC-V Patches for the 5.16 Merge Window, Part 1 > > What's "part 1" about this? > > This was sent on a Friday of the second week of the merge window. > > No way in hell is there going to be a "part 2" that I would possibly > accept at this stage. It's late as-is. Sorry that was misleading, I guess I just wrote "Part 1" as a matter of habit because it was the first merge window PR I sent out (it's late because I changed jobs and my test suite wasn't playing nice with the new computers). I wasn't planning on sending anything else for the merge window.
On Nov 12 2021, Palmer Dabbelt wrote:
> I wasn't planning on sending anything else for the merge window.
Not even the KBUILD_EXTMOD build fix?
Andreas.
On Fri, 12 Nov 2021 14:22:54 PST (-0800), schwab@linux-m68k.org wrote: > On Nov 12 2021, Palmer Dabbelt wrote: > >> I wasn't planning on sending anything else for the merge window. > > Not even the KBUILD_EXTMOD build fix? Sorry, I hadn't seen that one. I found some bugs in my test suite when getting it to run on the new machines so I've got some new failures I'm working through, which is sort of blocking up everything right now. Everything in this PR was tested the old way so I'm confident in it, but I usually do a merge with Linus' tree and test that before sending a PR. In hindsight it might have been better to skip that this time around, given all the headaches getting things up and running, but it's too late for that now. I'd like to get back on a more solid footing before trying to pick up more stuff -- I guess that's a pretty trivial fix, but anything in the build system can run into wrinkles (also looks like it was broken in 5.15, so it'll have to get backported).
The pull request you sent on Fri, 12 Nov 2021 09:32:15 -0800 (PST):
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.16-mw1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/b89f311d7e25eb246376ac10de46d6ecc6b6ed5c
Thank you!
The following changes since commit 3f2401f47d29d669e2cb137709d10dd4c156a02f: RISC-V: Add hypervisor extension related CSR defines (2021-10-04 04:54:55 -0400) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.16-mw1 for you to fetch changes up to ffa7a9141bb70702744a312f904b190ca064bdd7: riscv: defconfig: enable DRM_NOUVEAU (2021-10-27 14:36:09 -0700) ---------------------------------------------------------------- RISC-V Patches for the 5.16 Merge Window, Part 1 * Support for time namespaces in the VDSO, along with some associated cleanups. * Support for building rv32 randconfigs. * Improvements to the XIP port that allow larger kernels to function * Various device tree cleanups for both the SiFive and Microchip boards * A handful of defconfig updates, including enabling Nouveau. There are also various small cleanups. ---------------------------------------------------------------- Dimitri John Ledkov (1): riscv: set default pm_power_off to NULL Heinrich Schuchardt (1): riscv: defconfig: enable DRM_NOUVEAU Kefeng Wang (1): riscv/vdso: Drop unneeded part due to merge issue Krzysztof Kozlowski (11): dt-bindings: mmc: cdns: document Microchip MPFS MMC/SDHCI controller riscv: dts: microchip: drop duplicated nodes riscv: dts: microchip: fix board compatible riscv: dts: microchip: drop duplicated MMC/SDHC node riscv: dts: microchip: drop unused pinctrl-names riscv: dts: microchip: use vendor compatible for Cadence SD4HC riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible riscv: dts: sifive: fix Unleashed board compatible riscv: dts: sifive: drop duplicated nodes and properties in sifive riscv: dts: microchip: add missing compatibles for clint and plic riscv: dts: sifive: add missing compatible for plic Palmer Dabbelt (3): Merge remote-tracking branch 'palmer/riscv-vdso-cleanup' into for-next Merge tag 'for-riscv' of https://git.kernel.org/pub/scm/virt/kvm/kvm.git into for-next Merge tag 'riscv-sifive-dt-5.16' of git://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into for-next Randy Dunlap (1): riscv: add rv32 and rv64 randconfig build targets Tong Tiangen (1): riscv/vdso: Add support for time namespaces Vineet Gupta (1): riscv: mm: don't advertise 1 num_asid for 0 asid bits Vitaly Wool (1): riscv: remove .text section size limitation for XIP .../devicetree/bindings/mmc/cdns,sdhci.yaml | 1 + arch/riscv/Kconfig | 1 + arch/riscv/Makefile | 10 + .../dts/microchip/microchip-mpfs-icicle-kit.dts | 18 +- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 40 +--- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 10 +- .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 7 +- arch/riscv/configs/32-bit.config | 2 + arch/riscv/configs/64-bit.config | 2 + arch/riscv/configs/defconfig | 7 +- arch/riscv/include/asm/page.h | 2 + arch/riscv/include/asm/pgtable.h | 6 +- arch/riscv/include/asm/syscall.h | 1 + arch/riscv/include/asm/vdso.h | 13 +- arch/riscv/include/asm/vdso/gettimeofday.h | 7 + arch/riscv/kernel/head.S | 12 + arch/riscv/kernel/reset.c | 12 +- arch/riscv/kernel/syscall_table.c | 1 - arch/riscv/kernel/vdso.c | 261 +++++++++++++++++---- arch/riscv/kernel/vdso/vdso.lds.S | 6 +- arch/riscv/kernel/vmlinux-xip.lds.S | 10 +- arch/riscv/mm/context.c | 8 +- arch/riscv/mm/init.c | 7 +- 24 files changed, 311 insertions(+), 135 deletions(-) create mode 100644 arch/riscv/configs/32-bit.config create mode 100644 arch/riscv/configs/64-bit.config