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[GIT,PULL] RISC-V Patches for the 5.2 Merge Window, Part 1

Message ID mhng-d6bbd5f4-7409-4d3e-94a0-7ff0c6a71c9e@palmer-si-x1e (mailing list archive)
State New, archived
Headers show
Series [GIT,PULL] RISC-V Patches for the 5.2 Merge Window, Part 1 | expand

Pull-request

git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git tags/riscv-for-linus-5.2-mw0

Message

Palmer Dabbelt May 15, 2019, 5:39 p.m. UTC 
The following changes since commit 085b7755808aa11f78ab9377257e1dad2e6fa4bb:

  Linux 5.1-rc6 (2019-04-21 10:45:57 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git tags/riscv-for-linus-5.2-mw0

for you to fetch changes up to e23fc917f04ffac8c156fdb4ee8b56f3867fa50b:

  RISC-V: Avoid using invalid intermediate translations (2019-05-08 15:06:18 -0700)

----------------------------------------------------------------
RISC-V Patches for the 5.2 Merge Window, Part 1

This patch set contains an assortment of RISC-V related patches that I'd
like to target for the 5.2 merge window.  Most of the patches are
cleanups, but there are a handful of user-visible changes:

* The nosmp and nr_cpus command-line arguments are now supported, which
  work like normal.
* The SBI console no longer installs itself as a preferred console, we
  rely on standard mechanisms (/chosen, command-line, hueristics)
  instead.
* sfence_remove_sfence_vma{,_asid} now pass their arguments along to the
  SBI call.
* Modules now support BUG().
* A missing sfence.vma during boot has been added.  This bug only
  manifests during boot.

I've only tested this on QEMU again, as I didn't have time to get things
running on the Unleashed.  The latest master from this morning merges in
cleanly and passes the tests as well.

----------------------------------------------------------------
Anup Patel (4):
      RISC-V: Use tabs to align macro values in asm/csr.h
      RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
      RISC-V: Access CSRs using CSR numbers
      tty: Don't force RISCV SBI console as preferred console

Atish Patra (4):
      RISC-V: Add RISC-V specific arch_match_cpu_phys_id
      RISC-V: Implement nosmp commandline option.
      RISC-V: Support nr_cpus command line option.
      RISC-V: Fix minor checkpatch issues.

Christoph Hellwig (11):
      riscv: use asm-generic/extable.h
      riscv: turn mm_segment_t into a struct
      riscv: remove unreachable big endian code
      riscv: remove CONFIG_RISCV_ISA_A
      riscv: clear all pending interrupts when booting
      riscv: simplify the stack pointer setup in head.S
      riscv: cleanup the parse_dtb calling conventions
      riscv: remove unreachable !HAVE_FUNCTION_GRAPH_RET_ADDR_PTR code
      riscv: remove duplicate macros from ptrace.h
      riscv: print the unexpected interrupt cause
      riscv: call pm_power_off from machine_halt / machine_power_off

Gary Guo (3):
      riscv: move flush_icache_{all,mm} to cacheflush.c
      riscv: move switch_mm to its own file
      riscv: fix sbi_remote_sfence_vma{,_asid}.

Guo Ren (1):
      riscv/signal: Fixup additional syscall restarting

Nick Desaulniers (1):
      riscv: vdso: drop unnecessary cc-ldoption

Palmer Dabbelt (1):
      RISC-V: Avoid using invalid intermediate translations

Vincent Chen (3):
      riscv: support trap-based WARN()
      riscv: Add the support for c.ebreak check in is_valid_bugaddr()
      riscv: Support BUG() in kernel module

 arch/riscv/Kconfig                   |   6 +-
 arch/riscv/Makefile                  |   5 +-
 arch/riscv/include/asm/Kbuild        |   1 +
 arch/riscv/include/asm/bug.h         |  35 ++++++----
 arch/riscv/include/asm/cacheflush.h  |   2 +-
 arch/riscv/include/asm/csr.h         | 123 ++++++++++++++++++++++-------------
 arch/riscv/include/asm/elf.h         |   6 --
 arch/riscv/include/asm/futex.h       |  13 ----
 arch/riscv/include/asm/irqflags.h    |  10 +--
 arch/riscv/include/asm/mmu_context.h |  59 +----------------
 arch/riscv/include/asm/ptrace.h      |  21 ++----
 arch/riscv/include/asm/sbi.h         |  19 ++++--
 arch/riscv/include/asm/thread_info.h |   4 +-
 arch/riscv/include/asm/uaccess.h     |  28 +++-----
 arch/riscv/kernel/asm-offsets.c      |   3 -
 arch/riscv/kernel/cpu.c              |   3 +-
 arch/riscv/kernel/entry.S            |  22 +++----
 arch/riscv/kernel/head.S             |  33 ++++++----
 arch/riscv/kernel/irq.c              |  19 ++----
 arch/riscv/kernel/perf_event.c       |   4 +-
 arch/riscv/kernel/reset.c            |  15 +++--
 arch/riscv/kernel/setup.c            |   6 +-
 arch/riscv/kernel/signal.c           |   6 ++
 arch/riscv/kernel/smp.c              |  61 +++--------------
 arch/riscv/kernel/smpboot.           |   0
 arch/riscv/kernel/smpboot.c          |  22 ++++++-
 arch/riscv/kernel/stacktrace.c       |  14 ++--
 arch/riscv/kernel/traps.c            |  30 ++++++---
 arch/riscv/kernel/vdso/Makefile      |   2 +-
 arch/riscv/mm/Makefile               |   1 +
 arch/riscv/mm/cacheflush.c           |  61 +++++++++++++++++
 arch/riscv/mm/context.c              |  69 ++++++++++++++++++++
 arch/riscv/mm/fault.c                |   6 +-
 drivers/tty/hvc/hvc_riscv_sbi.c      |   1 -
 34 files changed, 390 insertions(+), 320 deletions(-)
 create mode 100644 arch/riscv/kernel/smpboot.
 create mode 100644 arch/riscv/mm/context.c

Comments

Atish Patra May 15, 2019, 7:08 p.m. UTC | #1 
On 5/15/19 10:40 AM, Palmer Dabbelt wrote:
> The following changes since commit 085b7755808aa11f78ab9377257e1dad2e6fa4bb:
> 
>    Linux 5.1-rc6 (2019-04-21 10:45:57 -0700)
> 
> are available in the Git repository at:
> 
>    git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git tags/riscv-for-linus-5.2-mw0
> 
> for you to fetch changes up to e23fc917f04ffac8c156fdb4ee8b56f3867fa50b:
> 
>    RISC-V: Avoid using invalid intermediate translations (2019-05-08 15:06:18 -0700)
> 
> ----------------------------------------------------------------
> RISC-V Patches for the 5.2 Merge Window, Part 1
> 
> This patch set contains an assortment of RISC-V related patches that I'd
> like to target for the 5.2 merge window.  Most of the patches are
> cleanups, but there are a handful of user-visible changes:
> 
> * The nosmp and nr_cpus command-line arguments are now supported, which
>    work like normal.
> * The SBI console no longer installs itself as a preferred console, we
>    rely on standard mechanisms (/chosen, command-line, hueristics)
>    instead.
> * sfence_remove_sfence_vma{,_asid} now pass their arguments along to the
>    SBI call.
> * Modules now support BUG().
> * A missing sfence.vma during boot has been added.  This bug only
>    manifests during boot.
> 
> I've only tested this on QEMU again, as I didn't have time to get things
> running on the Unleashed.  The latest master from this morning merges in
> cleanly and passes the tests as well.
> 
> ----------------------------------------------------------------
> Anup Patel (4):
>        RISC-V: Use tabs to align macro values in asm/csr.h
>        RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
>        RISC-V: Access CSRs using CSR numbers
>        tty: Don't force RISCV SBI console as preferred console
> 
> Atish Patra (4):
>        RISC-V: Add RISC-V specific arch_match_cpu_phys_id
>        RISC-V: Implement nosmp commandline option.
>        RISC-V: Support nr_cpus command line option.
>        RISC-V: Fix minor checkpatch issues.
> 
> Christoph Hellwig (11):
>        riscv: use asm-generic/extable.h
>        riscv: turn mm_segment_t into a struct
>        riscv: remove unreachable big endian code
>        riscv: remove CONFIG_RISCV_ISA_A
>        riscv: clear all pending interrupts when booting
>        riscv: simplify the stack pointer setup in head.S
>        riscv: cleanup the parse_dtb calling conventions
>        riscv: remove unreachable !HAVE_FUNCTION_GRAPH_RET_ADDR_PTR code
>        riscv: remove duplicate macros from ptrace.h
>        riscv: print the unexpected interrupt cause
>        riscv: call pm_power_off from machine_halt / machine_power_off
> 
> Gary Guo (3):
>        riscv: move flush_icache_{all,mm} to cacheflush.c
>        riscv: move switch_mm to its own file
>        riscv: fix sbi_remote_sfence_vma{,_asid}.
> 
> Guo Ren (1):
>        riscv/signal: Fixup additional syscall restarting
> 
> Nick Desaulniers (1):
>        riscv: vdso: drop unnecessary cc-ldoption
> 
> Palmer Dabbelt (1):
>        RISC-V: Avoid using invalid intermediate translations
> 
> Vincent Chen (3):
>        riscv: support trap-based WARN()
>        riscv: Add the support for c.ebreak check in is_valid_bugaddr()
>        riscv: Support BUG() in kernel module
> 
>   arch/riscv/Kconfig                   |   6 +-
>   arch/riscv/Makefile                  |   5 +-
>   arch/riscv/include/asm/Kbuild        |   1 +
>   arch/riscv/include/asm/bug.h         |  35 ++++++----
>   arch/riscv/include/asm/cacheflush.h  |   2 +-
>   arch/riscv/include/asm/csr.h         | 123 ++++++++++++++++++++++-------------
>   arch/riscv/include/asm/elf.h         |   6 --
>   arch/riscv/include/asm/futex.h       |  13 ----
>   arch/riscv/include/asm/irqflags.h    |  10 +--
>   arch/riscv/include/asm/mmu_context.h |  59 +----------------
>   arch/riscv/include/asm/ptrace.h      |  21 ++----
>   arch/riscv/include/asm/sbi.h         |  19 ++++--
>   arch/riscv/include/asm/thread_info.h |   4 +-
>   arch/riscv/include/asm/uaccess.h     |  28 +++-----
>   arch/riscv/kernel/asm-offsets.c      |   3 -
>   arch/riscv/kernel/cpu.c              |   3 +-
>   arch/riscv/kernel/entry.S            |  22 +++----
>   arch/riscv/kernel/head.S             |  33 ++++++----
>   arch/riscv/kernel/irq.c              |  19 ++----
>   arch/riscv/kernel/perf_event.c       |   4 +-
>   arch/riscv/kernel/reset.c            |  15 +++--
>   arch/riscv/kernel/setup.c            |   6 +-
>   arch/riscv/kernel/signal.c           |   6 ++
>   arch/riscv/kernel/smp.c              |  61 +++--------------
>   arch/riscv/kernel/smpboot.           |   0
>   arch/riscv/kernel/smpboot.c          |  22 ++++++-
>   arch/riscv/kernel/stacktrace.c       |  14 ++--
>   arch/riscv/kernel/traps.c            |  30 ++++++---
>   arch/riscv/kernel/vdso/Makefile      |   2 +-
>   arch/riscv/mm/Makefile               |   1 +
>   arch/riscv/mm/cacheflush.c           |  61 +++++++++++++++++
>   arch/riscv/mm/context.c              |  69 ++++++++++++++++++++
>   arch/riscv/mm/fault.c                |   6 +-
>   drivers/tty/hvc/hvc_riscv_sbi.c      |   1 -
>   34 files changed, 390 insertions(+), 320 deletions(-)
>   create mode 100644 arch/riscv/kernel/smpboot.

I think "smpboot." got added as a typo because of commit (RISC-V: 
Support nr_cpus command line option.).

Can you please update the PR directly or should I send a fixup patch?

Regards,
Atish
>   create mode 100644 arch/riscv/mm/context.c
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
Palmer Dabbelt May 16, 2019, 1:42 a.m. UTC | #2 
On Wed, 15 May 2019 12:08:36 PDT (-0700), atish.patra@wdc.com wrote:
> On 5/15/19 10:40 AM, Palmer Dabbelt wrote:
>> The following changes since commit 085b7755808aa11f78ab9377257e1dad2e6fa4bb:
>>
>>    Linux 5.1-rc6 (2019-04-21 10:45:57 -0700)
>>
>> are available in the Git repository at:
>>
>>    git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git tags/riscv-for-linus-5.2-mw0
>>
>> for you to fetch changes up to e23fc917f04ffac8c156fdb4ee8b56f3867fa50b:
>>
>>    RISC-V: Avoid using invalid intermediate translations (2019-05-08 15:06:18 -0700)
>>
>> ----------------------------------------------------------------
>> RISC-V Patches for the 5.2 Merge Window, Part 1
>>
>> This patch set contains an assortment of RISC-V related patches that I'd
>> like to target for the 5.2 merge window.  Most of the patches are
>> cleanups, but there are a handful of user-visible changes:
>>
>> * The nosmp and nr_cpus command-line arguments are now supported, which
>>    work like normal.
>> * The SBI console no longer installs itself as a preferred console, we
>>    rely on standard mechanisms (/chosen, command-line, hueristics)
>>    instead.
>> * sfence_remove_sfence_vma{,_asid} now pass their arguments along to the
>>    SBI call.
>> * Modules now support BUG().
>> * A missing sfence.vma during boot has been added.  This bug only
>>    manifests during boot.
>>
>> I've only tested this on QEMU again, as I didn't have time to get things
>> running on the Unleashed.  The latest master from this morning merges in
>> cleanly and passes the tests as well.
>>
>> ----------------------------------------------------------------
>> Anup Patel (4):
>>        RISC-V: Use tabs to align macro values in asm/csr.h
>>        RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
>>        RISC-V: Access CSRs using CSR numbers
>>        tty: Don't force RISCV SBI console as preferred console
>>
>> Atish Patra (4):
>>        RISC-V: Add RISC-V specific arch_match_cpu_phys_id
>>        RISC-V: Implement nosmp commandline option.
>>        RISC-V: Support nr_cpus command line option.
>>        RISC-V: Fix minor checkpatch issues.
>>
>> Christoph Hellwig (11):
>>        riscv: use asm-generic/extable.h
>>        riscv: turn mm_segment_t into a struct
>>        riscv: remove unreachable big endian code
>>        riscv: remove CONFIG_RISCV_ISA_A
>>        riscv: clear all pending interrupts when booting
>>        riscv: simplify the stack pointer setup in head.S
>>        riscv: cleanup the parse_dtb calling conventions
>>        riscv: remove unreachable !HAVE_FUNCTION_GRAPH_RET_ADDR_PTR code
>>        riscv: remove duplicate macros from ptrace.h
>>        riscv: print the unexpected interrupt cause
>>        riscv: call pm_power_off from machine_halt / machine_power_off
>>
>> Gary Guo (3):
>>        riscv: move flush_icache_{all,mm} to cacheflush.c
>>        riscv: move switch_mm to its own file
>>        riscv: fix sbi_remote_sfence_vma{,_asid}.
>>
>> Guo Ren (1):
>>        riscv/signal: Fixup additional syscall restarting
>>
>> Nick Desaulniers (1):
>>        riscv: vdso: drop unnecessary cc-ldoption
>>
>> Palmer Dabbelt (1):
>>        RISC-V: Avoid using invalid intermediate translations
>>
>> Vincent Chen (3):
>>        riscv: support trap-based WARN()
>>        riscv: Add the support for c.ebreak check in is_valid_bugaddr()
>>        riscv: Support BUG() in kernel module
>>
>>   arch/riscv/Kconfig                   |   6 +-
>>   arch/riscv/Makefile                  |   5 +-
>>   arch/riscv/include/asm/Kbuild        |   1 +
>>   arch/riscv/include/asm/bug.h         |  35 ++++++----
>>   arch/riscv/include/asm/cacheflush.h  |   2 +-
>>   arch/riscv/include/asm/csr.h         | 123 ++++++++++++++++++++++-------------
>>   arch/riscv/include/asm/elf.h         |   6 --
>>   arch/riscv/include/asm/futex.h       |  13 ----
>>   arch/riscv/include/asm/irqflags.h    |  10 +--
>>   arch/riscv/include/asm/mmu_context.h |  59 +----------------
>>   arch/riscv/include/asm/ptrace.h      |  21 ++----
>>   arch/riscv/include/asm/sbi.h         |  19 ++++--
>>   arch/riscv/include/asm/thread_info.h |   4 +-
>>   arch/riscv/include/asm/uaccess.h     |  28 +++-----
>>   arch/riscv/kernel/asm-offsets.c      |   3 -
>>   arch/riscv/kernel/cpu.c              |   3 +-
>>   arch/riscv/kernel/entry.S            |  22 +++----
>>   arch/riscv/kernel/head.S             |  33 ++++++----
>>   arch/riscv/kernel/irq.c              |  19 ++----
>>   arch/riscv/kernel/perf_event.c       |   4 +-
>>   arch/riscv/kernel/reset.c            |  15 +++--
>>   arch/riscv/kernel/setup.c            |   6 +-
>>   arch/riscv/kernel/signal.c           |   6 ++
>>   arch/riscv/kernel/smp.c              |  61 +++--------------
>>   arch/riscv/kernel/smpboot.           |   0
>>   arch/riscv/kernel/smpboot.c          |  22 ++++++-
>>   arch/riscv/kernel/stacktrace.c       |  14 ++--
>>   arch/riscv/kernel/traps.c            |  30 ++++++---
>>   arch/riscv/kernel/vdso/Makefile      |   2 +-
>>   arch/riscv/mm/Makefile               |   1 +
>>   arch/riscv/mm/cacheflush.c           |  61 +++++++++++++++++
>>   arch/riscv/mm/context.c              |  69 ++++++++++++++++++++
>>   arch/riscv/mm/fault.c                |   6 +-
>>   drivers/tty/hvc/hvc_riscv_sbi.c      |   1 -
>>   34 files changed, 390 insertions(+), 320 deletions(-)
>>   create mode 100644 arch/riscv/kernel/smpboot.
>
> I think "smpboot." got added as a typo because of commit (RISC-V:
> Support nr_cpus command line option.).
>
> Can you please update the PR directly or should I send a fixup patch?

OK.  It looks like I dropped the L2 patches, which I was going to submit as
another PR.  Since I have to do that anyway, I think it's best to just drop
this one.

Linus: I'm not sure how to tag this PR as a mistake, so I'm going to just send
another one.  If this gets merged then I'll handle the follow-on.

>
> Regards,
> Atish
>>   create mode 100644 arch/riscv/mm/context.c
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>>
Linus Torvalds May 16, 2019, 1:49 a.m. UTC | #3 
On Wed, May 15, 2019 at 6:43 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> Linus: I'm not sure how to tag this PR as a mistake, so I'm going to just send
> another one.  If this gets merged then I'll handle the follow-on.

Just emailing in the same thread ends up with me hopefully seeing the
"oops, cancel pull request" before I actually pull, so you did the
right thing.

To make sure, you _could_ obviously also just force-remove the tag you
asked me to pull, so that if I miss an email any pull attempt of mine
would just fail.

.., and if were to have ended up pulling before you sent the cancel
email and/or removed the tag, it's obviously all too late, and then
we'd have to fix things up after the fact, but at least this time it
got caught in time.

            Linus
Palmer Dabbelt May 16, 2019, 1:56 a.m. UTC | #4 
On Wed, 15 May 2019 18:49:57 PDT (-0700), Linus Torvalds wrote:
> On Wed, May 15, 2019 at 6:43 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> Linus: I'm not sure how to tag this PR as a mistake, so I'm going to just send
>> another one.  If this gets merged then I'll handle the follow-on.
>
> Just emailing in the same thread ends up with me hopefully seeing the
> "oops, cancel pull request" before I actually pull, so you did the
> right thing.
>
> To make sure, you _could_ obviously also just force-remove the tag you
> asked me to pull, so that if I miss an email any pull attempt of mine
> would just fail.

Ah, OK, I hadn't thought of that one.

> .., and if were to have ended up pulling before you sent the cancel
> email and/or removed the tag, it's obviously all too late, and then
> we'd have to fix things up after the fact, but at least this time it
> got caught in time.

Ya, that's fine.  It's just an extra 0-length file that doesn't get built
("file." instead of "file.c"), which explains how it went unnoticed.  That
said, it's a bit of an embarassment and I wanted to submit two more patches
anyway so I was going to send another PR.  The rebased patches are sitting on
my for-next now, I'll send them up tomorrow unless someone points something
out.

Thanks for the quick reply!