| Message ID | mhng-f80b6a8e-79e3-486b-95e4-18c04a1be0dd@palmer-ri-x1c9 (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | [GIT,PULL] RISC-V Fixes for 6.5-rc8 | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/apply | fail | Pull to for-next failed |
| conchuod/tree_selection | success | Pull request for for-next |
The pull request you sent on Fri, 25 Aug 2023 06:16:41 -0700 (PDT):
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.5-rc8
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/4942fed84b98cfb71d3cdff1a3df0072a57bbdfa
Thank you!
The following changes since commit ca09f772cccaeec4cd05a21528c37a260aa2dd2c: riscv: Handle zicsr/zifencei issue between gcc and binutils (2023-08-16 07:39:38 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-6.5-rc8 for you to fetch changes up to ef21fa7c198e04f3d3053b1c5b5f2b4b225c3350: riscv: Fix build errors using binutils2.37 toolchains (2023-08-24 12:35:20 -0700) ---------------------------------------------------------------- RISC-V Fixes for 6.5-rc8 * The vector ucontext extension has been extended with vlenb. * The vector registers ELF core dump note type has been changed to avoid aliasing with the CSR type used in embedded systems. * Support for accessing vector registers via ptrace() has been reverted. * Another build fix for the ISA spec changes around Zifencei/Zicsr that manifests on some systems built with binutils-2.37 and gcc-11.2. ---------------------------------------------------------------- This is obviously not ideal, particularly for something this late in the cycle. Unfortunately we found some uABI issues in the vector support while reviewing the GDB port, which has triggered a revert -- probably a good sign we should have reviewed GDB before merging this, I guess I just dropped the ball because I was so worried about the context extension and libc suff I forgot. Hence the late revert. There's some risk here as we're still exposing the vector context for signal handlers, but changing that would have meant reverting all of the vector support. The issues we've found so far have been fixed already and they weren't absolute showstoppers, so we're essentially just playing it safe by holding ptrace support for another release (or until we get through a proper userspace code review). So sorry for the churn, I'll try to be more careful next time. ---------------------------------------------------------------- Andy Chiu (1): RISC-V: vector: export VLENB csr in __sc_riscv_v_state Mingzheng Xing (1): riscv: Fix build errors using binutils2.37 toolchains Palmer Dabbelt (2): RISC-V: Remove ptrace support for vectors Merge patch series "riscv: fix ptrace and export VLENB" arch/riscv/Kconfig | 8 ++--- arch/riscv/include/asm/vector.h | 3 +- arch/riscv/include/uapi/asm/ptrace.h | 1 + arch/riscv/kernel/ptrace.c | 69 ------------------------------------ include/uapi/linux/elf.h | 1 - 5 files changed, 7 insertions(+), 75 deletions(-)