| Message ID | tencent_01F8E0050FB4B11CC170C3639E43F41A1709@qq.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | docs: riscv: Some clarifies on hwprobe misaligned performance | expand |
On Thu, May 23, 2024 at 8:36 PM Yangyu Chen <cyy@cyyself.name> wrote: > > Since the value in KEY_CPUPERF_0 is not bitmask, remove the wrong code > in hwprobe.h. > > Signed-off-by: Yangyu Chen <cyy@cyyself.name> I'd expect a Fixes tag, and ideally some discussion on the reasoning and ramifications of this change. I posted the other possible fix, declaring a new key, at [1], mostly so we could see the two options and discuss. I'm okay with either patch. -Evan [1] https://lore.kernel.org/lkml/20240529182649.2635123-1-evan@rivosinc.com/T/#u > --- > arch/riscv/include/asm/hwprobe.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > index 630507dff5ea..f24cad22bbe1 100644 > --- a/arch/riscv/include/asm/hwprobe.h > +++ b/arch/riscv/include/asm/hwprobe.h > @@ -20,7 +20,6 @@ static inline bool hwprobe_key_is_bitmask(__s64 key) > switch (key) { > case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: > case RISCV_HWPROBE_KEY_IMA_EXT_0: > - case RISCV_HWPROBE_KEY_CPUPERF_0: > return true; > } > > -- > 2.45.1 >
diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 630507dff5ea..f24cad22bbe1 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -20,7 +20,6 @@ static inline bool hwprobe_key_is_bitmask(__s64 key) switch (key) { case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: case RISCV_HWPROBE_KEY_IMA_EXT_0: - case RISCV_HWPROBE_KEY_CPUPERF_0: return true; }
Since the value in KEY_CPUPERF_0 is not bitmask, remove the wrong code in hwprobe.h. Signed-off-by: Yangyu Chen <cyy@cyyself.name> --- arch/riscv/include/asm/hwprobe.h | 1 - 1 file changed, 1 deletion(-)