| Message ID | tencent_221A82C2DAF38E66B85B313221958DDD7C08@qq.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] riscv: allow case-insensitive ISA string parsing | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/cover_letter | success | Single patches do not need cover letters |
| conchuod/tree_selection | success | Guessed tree name to be for-next at HEAD 310c33dc7a12 |
| conchuod/fixes_present | success | Fixes tag not required for -next series |
| conchuod/maintainers_pattern | success | MAINTAINERS pattern errors before the patch: 1 and now 1 |
| conchuod/verify_signedoff | success | Signed-off-by tag matches author and committer |
| conchuod/kdoc | success | Errors and warnings before: 0 this patch: 0 |
| conchuod/build_rv64_clang_allmodconfig | success | Errors and warnings before: 18 this patch: 18 |
| conchuod/module_param | success | Was 0 now: 0 |
| conchuod/build_rv64_gcc_allmodconfig | success | Errors and warnings before: 18 this patch: 18 |
| conchuod/build_rv32_defconfig | success | Build OK |
| conchuod/dtb_warn_rv64 | success | Errors and warnings before: 3 this patch: 3 |
| conchuod/header_inline | success | No static functions without inline keyword in header files |
| conchuod/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 14 lines checked |
| conchuod/source_inline | success | Was 0 now: 0 |
| conchuod/build_rv64_nommu_k210_defconfig | success | Build OK |
| conchuod/verify_fixes | success | No Fixes tag |
| conchuod/build_rv64_nommu_virt_defconfig | success | Build OK |
Hey Yangyu Chen, On Tue, Apr 25, 2023 at 08:00:16PM +0800, Yangyu Chen wrote: > After allowing case-insensitive ISA string parsing in the kernel code, > the docs should be updated. As I pointed out in my reply to your cover letter [1], I don't think this patch is backwards compatible, and should instead be fixed in rocket-chip's codebase, where it appears the capital letters were added without actually testing the output against the binding. If we allow caps here, booting old kernels with new devicetrees may experience the crash you mention in your cover letter. NAK, on the basis that this should be fixed in rocket-chip (or any other core-generator that outputs invalid devicetrees). Otherwise, the $subject doesn't match what is used for dt-bindings (use `git log --oneline -- /path/to/file` for examples) nor did you CC the output of get_maintainer.pl, with the devicetree maintainers notably being absent. Cheers, Conor. 1 - https://lore.kernel.org/linux-riscv/20230425-flyable-prompter-5b1e4cebf9db@wendy/ > Signed-off-by: Yangyu Chen <cyy@cyyself.name> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 001931d526ec..70afd1e8638b 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -79,11 +79,10 @@ properties: > User-Level ISA document, available from > https://riscv.org/specifications/ > > - While the isa strings in ISA specification are case > - insensitive, letters in the riscv,isa string must be all > - lowercase to simplify parsing. > + According to RISC-V ISA specification, the isa strings are > + case insensitive. > $ref: "/schemas/types.yaml#/definitions/string" > - pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ > + pattern: (?i)^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ > > # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here > timebase-frequency: false > -- > 2.40.0 >
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 001931d526ec..70afd1e8638b 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -79,11 +79,10 @@ properties: User-Level ISA document, available from https://riscv.org/specifications/ - While the isa strings in ISA specification are case - insensitive, letters in the riscv,isa string must be all - lowercase to simplify parsing. + According to RISC-V ISA specification, the isa strings are + case insensitive. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + pattern: (?i)^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false
After allowing case-insensitive ISA string parsing in the kernel code, the docs should be updated. Signed-off-by: Yangyu Chen <cyy@cyyself.name> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)