Message ID | 20190617073252.27810-71-jagan@amarulasolutions.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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bh=IJlTrExUV036P/BMRgn4pTMf63sVmYGkjOW1YSSrKmc=; b=MOnSOIuuXLB4R/7YAM3EGFX2wserKYHr7KIW26ccDfqCM/83GeUL3MtSZAzkmRLjGb CGyGzBv75kcySxp7HvmuYCWTD6Td+Igj0ANC7oxirDtxsOEqLD+AkMNWERiOkOWxl9xD uHDO9aMYd7crb/jD4BA5zYOi67dbGbAb4Tz77mTTaod26+dkpViPtHcsX3fpIBq8bK2v kHK2TTRxfUwV5oy6+5aYyB5kLw3FQGtsxvbcKii5XAnIRoAxIjemCurpU1GLyr73xpSK YmrLoFCe2u0ABUljGbu0n4nGo0Z1/i4FAf5yG1qtEyQUsi6lIpibHvTNaTDq5y92SkQt 1xaQ== X-Gm-Message-State: APjAAAUTdiE/zer/9pAL+obFdZ0R1DtPe4yCATM1UQ3CVIb8Dgew9XZ+ uYaFktTKV//0U0qhcIk3GYvGEw== X-Google-Smtp-Source: APXvYqz/92GSJfV9kbMIR2t9eSiuX76F1aMFO9AAUYUiRtQMNTTibEoY9tVm6gol+bCWmXXHqrez9A== X-Received: by 2002:a17:902:f216:: with SMTP id gn22mr88263731plb.118.1560757213677; Mon, 17 Jun 2019 00:40:13 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.245]) by smtp.gmail.com with ESMTPSA id m41sm15205998pje.18.2019.06.17.00.40.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 00:40:13 -0700 (PDT) From: Jagan Teki <jagan@amarulasolutions.com> To: Simon Glass <sjg@chromium.org>, Philipp Tomsich <philipp.tomsich@theobroma-systems.com>, Kever Yang <kever.yang@rock-chips.com>, YouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de Subject: [PATCH v2 70/99] ram: rk3399: Configure tsel write ca for lpddr4 Date: Mon, 17 Jun 2019 13:02:23 +0530 Message-Id: <20190617073252.27810-71-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190617073252.27810-1-jagan@amarulasolutions.com> References: <20190617073252.27810-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190617_004014_304602_1C4BB0E0 X-CRM114-Status: GOOD ( 11.91 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms <linux-rockchip.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-rockchip>, <mailto:linux-rockchip-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-rockchip/> List-Post: <mailto:linux-rockchip@lists.infradead.org> List-Help: <mailto:linux-rockchip-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-rockchip>, <mailto:linux-rockchip-request@lists.infradead.org?subject=subscribe> Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki <jagan@amarulasolutions.com>, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" <linux-rockchip-bounces@lists.infradead.org> Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP |
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ram: rk3399: Add LPDDR4 support
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diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index e03181fbc9..41dd19a9e6 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -502,9 +502,18 @@ static void set_ds_odt(const struct chan_info *chan, /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4); - clrsetbits_le32(&denali_phy[544], 0xff, reg_value); - clrsetbits_le32(&denali_phy[672], 0xff, reg_value); - clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) { + /* LPDDR4 these register read always return 0, so + * can not use clrsetbits_le32(), need to write32 + */ + writel((0x300 << 8) | reg_value, &denali_phy[544]); + writel((0x300 << 8) | reg_value, &denali_phy[672]); + writel((0x300 << 8) | reg_value, &denali_phy[800]); + } else { + clrsetbits_le32(&denali_phy[544], 0xff, reg_value); + clrsetbits_le32(&denali_phy[672], 0xff, reg_value); + clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + } /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ clrsetbits_le32(&denali_phy[928], 0xff, reg_value);