Message ID | 20190617073252.27810-84-jagan@amarulasolutions.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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bh=3scj5tpu65v2n66++2cTbZLzQWWaAK5Y+ewcl6Aa8Eo=; b=dzzSv1/3ItuQ2MGQksTGt8uHw1+obqpU0i7UEgvZjQAF0HwNeL7Gwb5DPgk678zb/Y NQZoBUPWClGYr2b+ldnqiDaz9kRATINVEeZf5hQNPCdKmyTxMtZa2nzDBT4k/lBe19A2 unDgnhpdcOUf5EWW4+4j41Iu3LcJ9otIbtERpSJ9iHRm0T0mmHyRWM//nWTuUYhJMQpN +0B7Kgbc4hA1YUilhky0js0jffKyh39BPp1GhxBBoMKzAlgKEGJ13S0HNu9XDBY92B2v PB4P2S91KCdMb92fXzm2w23MACjacEzvwPoTTIkQ6pFU1zYL1Xh1Hfw0dlHJ2vPQBkcp pfhQ== X-Gm-Message-State: APjAAAWM3H1Y81EOt2BT81qrrB74RNb3AmWnctLh3vlZ5x9fOBhZTKZc tBkMEH8eEhiAt+dMS9dfyyGhUg== X-Google-Smtp-Source: APXvYqz/ZXE2q4c55juPsGQ+wHmSreuPKQyIVxDW9K35zDwdJuGsjBbFmFLEQ4ibJf/MRF3yLnpHrA== X-Received: by 2002:a63:e502:: with SMTP id r2mr19502433pgh.261.1560757256451; Mon, 17 Jun 2019 00:40:56 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.245]) by smtp.gmail.com with ESMTPSA id m41sm15205998pje.18.2019.06.17.00.40.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 00:40:56 -0700 (PDT) From: Jagan Teki <jagan@amarulasolutions.com> To: Simon Glass <sjg@chromium.org>, Philipp Tomsich <philipp.tomsich@theobroma-systems.com>, Kever Yang <kever.yang@rock-chips.com>, YouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de Subject: [PATCH v2 83/99] arm: include: rockchip: Add rk3399 pmu file Date: Mon, 17 Jun 2019 13:02:36 +0530 Message-Id: <20190617073252.27810-84-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190617073252.27810-1-jagan@amarulasolutions.com> References: <20190617073252.27810-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190617_004056_977559_4EED6B4C X-CRM114-Status: UNSURE ( 9.77 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms <linux-rockchip.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-rockchip>, <mailto:linux-rockchip-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-rockchip/> List-Post: <mailto:linux-rockchip@lists.infradead.org> List-Help: <mailto:linux-rockchip-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-rockchip>, <mailto:linux-rockchip-request@lists.infradead.org?subject=subscribe> Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Jagan Teki <jagan@amarulasolutions.com>, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" <linux-rockchip-bounces@lists.infradead.org> Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP |
Series |
ram: rk3399: Add LPDDR4 support
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expand
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diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h new file mode 100644 index 0000000000..f1096dccce --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd. + * + */ + +#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__ +#define __SOC_ROCKCHIP_RK3399_PMU_H__ + +struct rk3399_pmu_regs { + u32 pmu_wakeup_cfg[5]; + u32 pmu_pwrdn_con; + u32 pmu_pwrdn_st; + u32 pmu_pll_con; + u32 pmu_pwrmode_con; + u32 pmu_sft_con; + u32 pmu_int_con; + u32 pmu_int_st; + u32 pmu_gpio0_pos_int_con; + u32 pmu_gpio0_net_int_con; + u32 pmu_gpio1_pos_int_con; + u32 pmu_gpio1_net_int_con; + u32 pmu_gpio0_pos_int_st; + u32 pmu_gpio0_net_int_st; + u32 pmu_gpio1_pos_int_st; + u32 pmu_gpio1_net_int_st; + u32 pmu_pwrdn_inten; + u32 pmu_pwrdn_status; + u32 pmu_wakeup_status; + u32 pmu_bus_clr; + u32 pmu_bus_idle_req; + u32 pmu_bus_idle_st; + u32 pmu_bus_idle_ack; + u32 pmu_cci500_con; + u32 pmu_adb400_con; + u32 pmu_adb400_st; + u32 pmu_power_st; + u32 pmu_core_pwr_st; + u32 pmu_osc_cnt; + u32 pmu_plllock_cnt; + u32 pmu_pllrst_cnt; + u32 pmu_stable_cnt; + u32 pmu_ddrio_pwron_cnt; + u32 pmu_wakeup_rst_clr_cnt; + u32 pmu_ddr_sref_st; + u32 pmu_scu_l_pwrdn_cnt; + u32 pmu_scu_l_pwrup_cnt; + u32 pmu_scu_b_pwrdn_cnt; + u32 pmu_scu_b_pwrup_cnt; + u32 pmu_gpu_pwrdn_cnt; + u32 pmu_gpu_pwrup_cnt; + u32 pmu_center_pwrdn_cnt; + u32 pmu_center_pwrup_cnt; + u32 pmu_timeout_cnt; + u32 pmu_cpu0apm_con; + u32 pmu_cpu1apm_con; + u32 pmu_cpu2apm_con; + u32 pmu_cpu3apm_con; + u32 pmu_cpu0bpm_con; + u32 pmu_cpu1bpm_con; + u32 pmu_noc_auto_ena; + u32 pmu_pwrdn_con1; + u32 reserved0[0x4]; + u32 pmu_sys_reg_reg0; + u32 pmu_sys_reg_reg1; + u32 pmu_sys_reg_reg2; + u32 pmu_sys_reg_reg3; +}; + +check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc); + +#endif /* __SOC_ROCKCHIP_RK3399_PMU_H__ */