diff mbox series

[v3,32/57] ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1

Message ID 20190716115745.12585-33-jagan@amarulasolutions.com (mailing list archive)
State New, archived
Headers show
Series ram: rk3399: Add LPDDR4 support | expand

Commit Message

Jagan Teki July 16, 2019, 11:57 a.m. UTC 
The hardware for LPDDR4 with
- CLK0P/N connect to lower 16-bits
- CLK1P/N connect to higher 16-bits

and usually dfi dram clk is configured via CLK1P/N, so
disabling dfi dram clk will disable the CLK1P/N as well.

So, add patch to not to disable dfi dram clk for lpddr4,
with rank 1.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
 drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

Comments

Kever Yang July 16, 2019, 1:14 p.m. UTC | #1 
On 2019/7/16 下午7:57, Jagan Teki wrote:
> The hardware for LPDDR4 with
> - CLK0P/N connect to lower 16-bits
> - CLK1P/N connect to higher 16-bits
>
> and usually dfi dram clk is configured via CLK1P/N, so
> disabling dfi dram clk will disable the CLK1P/N as well.
>
> So, add patch to not to disable dfi dram clk for lpddr4,
> with rank 1.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Signed-off-by: YouMin Chen <cym@rock-chips.com>

Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

Thanks,
  - Kever
> ---
>   drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++--
>   1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index 1050cbdb07..359ab0b826 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -1225,8 +1225,18 @@ static void dram_all_config(struct dram_info *dram,
>   		writel(noc_timing->ddrmode.d32,
>   		       &ddr_msch_regs->ddrmode);
>   
> -		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
> -		if (params->ch[channel].cap_info.rank == 1)
> +		/**
> +		 * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
> +		 *
> +		 * The hardware for LPDDR4 with
> +		 * - CLK0P/N connect to lower 16-bits
> +		 * - CLK1P/N connect to higher 16-bits
> +		 *
> +		 * dfi dram clk is configured via CLK1P/N, so disabling
> +		 * dfi dram clk will disable the CLK1P/N as well for lpddr4.
> +		 */
> +		if (params->ch[channel].cap_info.rank == 1 &&
> +		    params->base.dramtype != LPDDR4)
>   			setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
>   				     1 << 17);
>   	}
diff mbox series

Patch

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 1050cbdb07..359ab0b826 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1225,8 +1225,18 @@  static void dram_all_config(struct dram_info *dram,
 		writel(noc_timing->ddrmode.d32,
 		       &ddr_msch_regs->ddrmode);
 
-		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
-		if (params->ch[channel].cap_info.rank == 1)
+		/**
+		 * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
+		 *
+		 * The hardware for LPDDR4 with
+		 * - CLK0P/N connect to lower 16-bits
+		 * - CLK1P/N connect to higher 16-bits
+		 *
+		 * dfi dram clk is configured via CLK1P/N, so disabling
+		 * dfi dram clk will disable the CLK1P/N as well for lpddr4.
+		 */
+		if (params->ch[channel].cap_info.rank == 1 &&
+		    params->base.dramtype != LPDDR4)
 			setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
 				     1 << 17);
 	}