[v3,48/57] clk: rockchip: rk3399: Set 400MHz ddr clock

Commit Message

Jagan Teki July 16, 2019, 11:57 a.m. UTC

Add support for setting 400MHz ddr clock.

Signed-off-by: Jagan Teki <[e-mail]>
Signed-off-by: YouMin Chen <[e-mail]>
---
 drivers/clk/rockchip/clk_rk3399.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Kever Yang July 16, 2019, 1:19 p.m. UTC | #1

On 2019/7/16 下午7:57, Jagan Teki wrote:
> Add support for setting 400MHz ddr clock.
>
> Signed-off-by: Jagan Teki <[e-mail]>
> Signed-off-by: YouMin Chen <[e-mail]>

Reviewed-by: Kever Yang <[e-mail]>

Thanks,
  - Kever
> ---
>   drivers/clk/rockchip/clk_rk3399.c | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
> index 1de21c9f3e..79007b8682 100644
> --- a/drivers/clk/rockchip/clk_rk3399.c
> +++ b/drivers/clk/rockchip/clk_rk3399.c
> @@ -839,6 +839,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
>   		dpll_cfg = (struct pll_div)
>   		{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
>   		break;
> +	case 400 * MHz:
> +		dpll_cfg = (struct pll_div)
> +		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
> +		break;
>   	case 666 * MHz:
>   		dpll_cfg = (struct pll_div)
>   		{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};

Patch

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 1de21c9f3e..79007b8682 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -839,6 +839,10 @@  static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 		dpll_cfg = (struct pll_div)
 		{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
 		break;
+	case 400 * MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
+		break;
 	case 666 * MHz:
 		dpll_cfg = (struct pll_div)
 		{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};