| Message ID | 20221109100928.109478-3-vivek.2311@samsung.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/6] dt-bindings: Document the SYSREG specific compatibles found on FSD SoC | expand |
On 09/11/2022 11:09, Vivek Yadav wrote: > Whenever the data is transferred or stored on message ram, there are > inherent risks of it being lost or corruption known as single-bit errors. > > ECC constantly scans data as it is processed to the message ram, using a > method known as parity checking and raise the error signals for corruption. > > Add error correction code config property to enable/disable the > error correction code (ECC) functionality for Message RAM used to create > valid ECC checksums. > > Signed-off-by: Chandrasekar R <rcsekar@samsung.com> > Cc: devicetree@vger.kernel.org > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Rob Herring <robh+dt@kernel.org> > Signed-off-by: Vivek Yadav <vivek.2311@samsung.com> > --- > .../bindings/net/can/bosch,m_can.yaml | 31 +++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml > index 26aa0830eea1..91dc458ec33f 100644 > --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml > +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml > @@ -50,6 +50,12 @@ properties: > - const: hclk > - const: cclk > > + tesla,mram-ecc-cfg: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + description: > + Handle to system control region that contains the ECC INIT register > + and register offset to the ECC INIT register. That's not way to describe syscon phandle. Property name is ok. For the rest look at: https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42 Anyway, this looks like SoC-specific hack, so it does not really fit to the driver. You have to think of something generic. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index 26aa0830eea1..91dc458ec33f 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -50,6 +50,12 @@ properties: - const: hclk - const: cclk + tesla,mram-ecc-cfg: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Handle to system control region that contains the ECC INIT register + and register offset to the ECC INIT register. + bosch,mram-cfg: description: | Message RAM configuration data. @@ -149,4 +155,29 @@ examples: }; }; + # Example 2: m_can on the FSD SoC + - | + #include <dt-bindings/clock/fsd-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + can@14088000 { + compatible = "bosch,m_can"; + reg = <0x0 0x14088000 0x0 0x0200>, + <0x0 0x14080000 0x0 0x8000>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + pinctrl-names = "default"; + pinctrl-0 = <&m_can0_bus>; + clocks = <&clock_peric PERIC_MCAN0_IPCLKPORT_PCLK>, + <&clock_peric PERIC_MCAN0_IPCLKPORT_CCLK>; + clock-names = "hclk", "cclk"; + tesla,mram-ecc-cfg = <&sysreg_peric 0x708>; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; + }; ...