| Message ID | 1449904607-4060-2-git-send-email-dirk.behme@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Dirk, On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme <dirk.behme@gmail.com> wrote: > From: Geert Uytterhoeven <geert+renesas@glider.be> > > Add device nodes for the L2 caches, and link the CPU node to its L2 > cache node. > > The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as > 128 KiB x 16 ways). > > The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as > 32 KiB x 16 ways). > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Dirk Behme <dirk.behme@gmail.com> > --- > Note: Geert: I picked your patch from > > http://www.spinics.net/lists/arm-kernel/msg466628.html > > incoporated some review comments and rebased it against > > https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next renesas-next-20151211v2-v4.4-rc1 This is more or less what I have locally, except that I kept the latency properties, pending discussion. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 18.12.2015 12:03, Geert Uytterhoeven wrote: > Hi Dirk, > > On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme <dirk.behme@gmail.com> wrote: >> From: Geert Uytterhoeven <geert+renesas@glider.be> >> >> Add device nodes for the L2 caches, and link the CPU node to its L2 >> cache node. >> >> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as >> 128 KiB x 16 ways). >> >> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as >> 32 KiB x 16 ways). >> >> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> >> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> >> --- >> Note: Geert: I picked your patch from >> >> http://www.spinics.net/lists/arm-kernel/msg466628.html >> >> incoporated some review comments and rebased it against >> >> https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next renesas-next-20151211v2-v4.4-rc1 > > This is more or less what I have locally, except that I kept the latency > properties Hmm, maybe I missed anything, but the only part reading the latency I can find is arch/arm/mm/cache-l2x0.c [1] which isn't relevant for arm64? Best regards Dirk [1] ./arch/arm/mm/cache-l2x0.c:1042: of_property_read_u32(np, "arm,tag-latency", &tag); ./arch/arm/mm/cache-l2x0.c:1143: of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Dirk, On Fri, Dec 18, 2015 at 12:56 PM, Dirk Behme <dirk.behme@gmail.com> wrote: > On 18.12.2015 12:03, Geert Uytterhoeven wrote: >> On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme <dirk.behme@gmail.com> wrote: >>> From: Geert Uytterhoeven <geert+renesas@glider.be> >>> >>> Add device nodes for the L2 caches, and link the CPU node to its L2 >>> cache node. >>> >>> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as >>> 128 KiB x 16 ways). >>> >>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as >>> 32 KiB x 16 ways). >>> >>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> >>> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> >>> --- >>> Note: Geert: I picked your patch from >>> >>> http://www.spinics.net/lists/arm-kernel/msg466628.html >>> >>> incoporated some review comments and rebased it against >>> >>> https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next >>> renesas-next-20151211v2-v4.4-rc1 >> >> This is more or less what I have locally, except that I kept the latency >> properties > > Hmm, maybe I missed anything, but the only part reading the latency I can > find is > > arch/arm/mm/cache-l2x0.c > > [1] which isn't relevant for arm64? No driver using a property in DT is not a reason not to put the property in DT. The r8a7995 datasheet does contain the latency values to use. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-sh" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 18/12/15 13:33, Geert Uytterhoeven wrote: > Hi Dirk, > > On Fri, Dec 18, 2015 at 12:56 PM, Dirk Behme <dirk.behme@gmail.com> wrote: >> On 18.12.2015 12:03, Geert Uytterhoeven wrote: >>> On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme <dirk.behme@gmail.com> wrote: >>>> From: Geert Uytterhoeven <geert+renesas@glider.be> >>>> >>>> Add device nodes for the L2 caches, and link the CPU node to its L2 >>>> cache node. >>>> >>>> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as >>>> 128 KiB x 16 ways). >>>> >>>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as >>>> 32 KiB x 16 ways). >>>> >>>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> >>>> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> >>>> --- >>>> Note: Geert: I picked your patch from >>>> >>>> http://www.spinics.net/lists/arm-kernel/msg466628.html >>>> >>>> incoporated some review comments and rebased it against >>>> >>>> https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next >>>> renesas-next-20151211v2-v4.4-rc1 >>> >>> This is more or less what I have locally, except that I kept the latency >>> properties >> >> Hmm, maybe I missed anything, but the only part reading the latency I can >> find is >> >> arch/arm/mm/cache-l2x0.c >> >> [1] which isn't relevant for arm64? > > No driver using a property in DT is not a reason not to put the property in DT. > The r8a7995 datasheet does contain the latency values to use. > While I agree with that, I would avoid having these values for 2 reasons: 1. Others might blindly copy and expect these setting to done in Linux or any non-secure OS using DT which is clearly not possible on ARM64 2. Going by your argument, we usually have much more in datasheets which are not all in DT, so strictly speaking that's not a reason to have it here. Again I am not against it, just an opinion.
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 3633a2a..d63a70f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -39,6 +39,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; @@ -46,46 +47,61 @@ compatible = "arm,cortex-a57","arm,armv8"; reg = <0x1>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_2: cpu@2 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x2>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_3: cpu@3 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x3>; device_type = "cpu"; + next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a53_0: cpu@100 { compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x100>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; enable-method = "psci"; }; a53_1: cpu@101 { compatible = "arm,cortex-a53","arm,armv8"; reg = <0x101>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; enable-method = "psci"; }; a53_2: cpu@102 { compatible = "arm,cortex-a53","arm,armv8"; reg = <0x102>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; enable-method = "psci"; }; a53_3: cpu@103 { compatible = "arm,cortex-a53","arm,armv8"; reg = <0x103>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; enable-method = "psci"; }; }; + L2_CA57: cache-controller@0 { + compatible = "cache"; + }; + + L2_CA53: cache-controller@1 { + compatible = "cache"; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>;